kernel
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra Power Management Controller (PMC)
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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enum:
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- nvidia,tegra186-pmc
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- nvidia,tegra194-pmc
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- nvidia,tegra234-pmc
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reg:
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minItems: 4
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maxItems: 5
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reg-names:
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minItems: 4
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items:
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- const: pmc
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- const: wake
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- const: aotag
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- const: scratch
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- const: misc
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interrupt-controller: true
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"#interrupt-cells":
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description: Specifies the number of cells needed to encode an
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interrupt source. The value must be 2.
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const: 2
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nvidia,invert-interrupt:
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description: If present, inverts the PMU interrupt signal.
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$ref: /schemas/types.yaml#/definitions/flag
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if:
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properties:
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compatible:
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contains:
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const: nvidia,tegra186-pmc
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then:
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properties:
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reg:
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maxItems: 4
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reg-names:
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maxItems: 4
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else:
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properties:
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reg:
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minItems: 5
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reg-names:
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minItems: 5
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patternProperties:
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"^[a-z0-9]+-[a-z0-9]+$":
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if:
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type: object
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then:
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description: |
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These are pad configuration nodes. On Tegra SoCs a pad is a set of
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pins which are configured as a group. The pin grouping is a fixed
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attribute of the hardware. The PMC can be used to set pad power
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state and signaling voltage. A pad can be either in active or
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power down mode. The support for power state and signaling voltage
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configuration varies depending on the pad in question. 3.3 V and
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1.8 V signaling voltages are supported on pins where software
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controllable signaling voltage switching is available.
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Pad configurations are described with pin configuration nodes
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which are placed under the pmc node and they are referred to by
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the pinctrl client properties. For more information see
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Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
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The following pads are present on Tegra186:
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csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
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pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
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hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
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dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp,
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sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv
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The following pads are present on Tegra194:
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csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
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pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
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pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12,
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soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2,
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hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
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pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
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spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
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audio-hv, ao-hv
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properties:
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pins:
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$ref: /schemas/types.yaml#/definitions/string
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description: Must contain the name of the pad(s) to be
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configured.
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low-power-enable:
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description: Configure the pad into power down mode.
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$ref: /schemas/types.yaml#/definitions/flag
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low-power-disable:
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description: Configure the pad into active mode.
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$ref: /schemas/types.yaml#/definitions/flag
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power-source:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
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TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling
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voltages.
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The values are defined in
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include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
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The power state can be configured on all of the above pads
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except for ao-hv. Following pads have software configurable
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signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
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audio-hv, ao-hv.
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phandle: true
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required:
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- pins
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additionalProperties: false
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required:
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- compatible
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- reg
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- reg-names
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additionalProperties: false
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dependencies:
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interrupt-controller: ['#interrupt-cells']
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"#interrupt-cells":
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required:
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- interrupt-controller
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examples:
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- |
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#include <dt-bindings/clock/tegra186-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
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#include <dt-bindings/memory/tegra186-mc.h>
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#include <dt-bindings/reset/tegra186-reset.h>
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pmc@c3600000 {
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compatible = "nvidia,tegra186-pmc";
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reg = <0x0c360000 0x10000>,
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<0x0c370000 0x10000>,
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<0x0c380000 0x10000>,
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<0x0c390000 0x10000>;
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reg-names = "pmc", "wake", "aotag", "scratch";
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nvidia,invert-interrupt;
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sdmmc1_3v3: sdmmc1-3v3 {
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pins = "sdmmc1-hv";
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power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
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};
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sdmmc1_1v8: sdmmc1-1v8 {
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pins = "sdmmc1-hv";
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power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
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};
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};
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sdmmc1: mmc@3400000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x03400000 0x10000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
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<&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
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clock-names = "sdhci", "tmclk";
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resets = <&bpmp TEGRA186_RESET_SDMMC1>;
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reset-names = "sdhci";
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interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
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<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu TEGRA186_SID_SDMMC1>;
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pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
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pinctrl-0 = <&sdmmc1_3v3>;
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pinctrl-1 = <&sdmmc1_1v8>;
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};
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