kernel
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83468 changed files with 37938688 additions and 0 deletions
145
linux-6.8.1/include/linux/mfd/samsung/core.h
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145
linux-6.8.1/include/linux/mfd/samsung/core.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*/
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#ifndef __LINUX_MFD_SEC_CORE_H
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#define __LINUX_MFD_SEC_CORE_H
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/* Macros to represent minimum voltages for LDO/BUCK */
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#define MIN_3000_MV 3000000
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#define MIN_2500_MV 2500000
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#define MIN_2000_MV 2000000
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#define MIN_1800_MV 1800000
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#define MIN_1500_MV 1500000
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#define MIN_1400_MV 1400000
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#define MIN_1000_MV 1000000
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#define MIN_900_MV 900000
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#define MIN_850_MV 850000
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#define MIN_800_MV 800000
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#define MIN_750_MV 750000
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#define MIN_650_MV 650000
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#define MIN_600_MV 600000
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#define MIN_500_MV 500000
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/* Ramp delay in uV/us */
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#define RAMP_DELAY_12_MVUS 12000
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/* Macros to represent steps for LDO/BUCK */
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#define STEP_50_MV 50000
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#define STEP_25_MV 25000
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#define STEP_12_5_MV 12500
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#define STEP_6_25_MV 6250
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struct gpio_desc;
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enum sec_device_type {
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S5M8767X,
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S2MPA01,
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S2MPS11X,
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S2MPS13X,
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S2MPS14X,
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S2MPS15X,
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S2MPU02,
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};
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/**
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* struct sec_pmic_dev - s2m/s5m master device for sub-drivers
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* @dev: Master device of the chip
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* @pdata: Platform data populated with data from DTS
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* or board files
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* @regmap_pmic: Regmap associated with PMIC's I2C address
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* @i2c: I2C client of the main driver
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* @device_type: Type of device, matches enum sec_device_type
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* @irq_base: Base IRQ number for device, required for IRQs
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* @irq: Generic IRQ number for device
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* @irq_data: Runtime data structure for IRQ controller
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* @wakeup: Whether or not this is a wakeup device
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*/
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struct sec_pmic_dev {
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struct device *dev;
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struct sec_platform_data *pdata;
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struct regmap *regmap_pmic;
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struct i2c_client *i2c;
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unsigned long device_type;
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int irq;
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struct regmap_irq_chip_data *irq_data;
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};
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int sec_irq_init(struct sec_pmic_dev *sec_pmic);
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void sec_irq_exit(struct sec_pmic_dev *sec_pmic);
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int sec_irq_resume(struct sec_pmic_dev *sec_pmic);
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struct sec_platform_data {
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struct sec_regulator_data *regulators;
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struct sec_opmode_data *opmode;
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int num_regulators;
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int buck_gpios[3];
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int buck_ds[3];
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unsigned int buck2_voltage[8];
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bool buck2_gpiodvs;
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unsigned int buck3_voltage[8];
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bool buck3_gpiodvs;
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unsigned int buck4_voltage[8];
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bool buck4_gpiodvs;
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int buck_default_idx;
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int buck_ramp_delay;
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bool buck2_ramp_enable;
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bool buck3_ramp_enable;
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bool buck4_ramp_enable;
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int buck2_init;
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int buck3_init;
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int buck4_init;
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/* Whether or not manually set PWRHOLD to low during shutdown. */
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bool manual_poweroff;
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/* Disable the WRSTBI (buck voltage warm reset) when probing? */
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bool disable_wrstbi;
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};
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/**
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* sec_regulator_data - regulator data
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* @id: regulator id
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* @initdata: regulator init data (contraints, supplies, ...)
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*/
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struct sec_regulator_data {
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int id;
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struct regulator_init_data *initdata;
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struct device_node *reg_node;
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struct gpio_desc *ext_control_gpiod;
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};
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/*
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* sec_opmode_data - regulator operation mode data
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* @id: regulator id
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* @mode: regulator operation mode
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*/
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struct sec_opmode_data {
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int id;
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unsigned int mode;
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};
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/*
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* samsung regulator operation mode
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* SEC_OPMODE_OFF Regulator always OFF
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* SEC_OPMODE_ON Regulator always ON
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* SEC_OPMODE_LOWPOWER Regulator is on in low-power mode
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* SEC_OPMODE_SUSPEND Regulator is changed by PWREN pin
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* If PWREN is high, regulator is on
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* If PWREN is low, regulator is off
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*/
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enum sec_opmode {
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SEC_OPMODE_OFF,
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SEC_OPMODE_ON,
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SEC_OPMODE_LOWPOWER,
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SEC_OPMODE_SUSPEND,
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};
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#endif /* __LINUX_MFD_SEC_CORE_H */
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197
linux-6.8.1/include/linux/mfd/samsung/irq.h
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197
linux-6.8.1/include/linux/mfd/samsung/irq.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*/
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#ifndef __LINUX_MFD_SEC_IRQ_H
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#define __LINUX_MFD_SEC_IRQ_H
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enum s2mpa01_irq {
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S2MPA01_IRQ_PWRONF,
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S2MPA01_IRQ_PWRONR,
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S2MPA01_IRQ_JIGONBF,
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S2MPA01_IRQ_JIGONBR,
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S2MPA01_IRQ_ACOKBF,
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S2MPA01_IRQ_ACOKBR,
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S2MPA01_IRQ_PWRON1S,
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S2MPA01_IRQ_MRB,
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S2MPA01_IRQ_RTC60S,
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S2MPA01_IRQ_RTCA1,
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S2MPA01_IRQ_RTCA0,
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S2MPA01_IRQ_SMPL,
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S2MPA01_IRQ_RTC1S,
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S2MPA01_IRQ_WTSR,
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S2MPA01_IRQ_INT120C,
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S2MPA01_IRQ_INT140C,
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S2MPA01_IRQ_LDO3_TSD,
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S2MPA01_IRQ_B16_TSD,
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S2MPA01_IRQ_B24_TSD,
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S2MPA01_IRQ_B35_TSD,
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S2MPA01_IRQ_NR,
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};
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#define S2MPA01_IRQ_PWRONF_MASK (1 << 0)
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#define S2MPA01_IRQ_PWRONR_MASK (1 << 1)
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#define S2MPA01_IRQ_JIGONBF_MASK (1 << 2)
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#define S2MPA01_IRQ_JIGONBR_MASK (1 << 3)
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#define S2MPA01_IRQ_ACOKBF_MASK (1 << 4)
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#define S2MPA01_IRQ_ACOKBR_MASK (1 << 5)
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#define S2MPA01_IRQ_PWRON1S_MASK (1 << 6)
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#define S2MPA01_IRQ_MRB_MASK (1 << 7)
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#define S2MPA01_IRQ_RTC60S_MASK (1 << 0)
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#define S2MPA01_IRQ_RTCA1_MASK (1 << 1)
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#define S2MPA01_IRQ_RTCA0_MASK (1 << 2)
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#define S2MPA01_IRQ_SMPL_MASK (1 << 3)
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#define S2MPA01_IRQ_RTC1S_MASK (1 << 4)
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#define S2MPA01_IRQ_WTSR_MASK (1 << 5)
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#define S2MPA01_IRQ_INT120C_MASK (1 << 0)
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#define S2MPA01_IRQ_INT140C_MASK (1 << 1)
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#define S2MPA01_IRQ_LDO3_TSD_MASK (1 << 2)
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#define S2MPA01_IRQ_B16_TSD_MASK (1 << 3)
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#define S2MPA01_IRQ_B24_TSD_MASK (1 << 4)
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#define S2MPA01_IRQ_B35_TSD_MASK (1 << 5)
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enum s2mps11_irq {
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S2MPS11_IRQ_PWRONF,
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S2MPS11_IRQ_PWRONR,
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S2MPS11_IRQ_JIGONBF,
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S2MPS11_IRQ_JIGONBR,
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S2MPS11_IRQ_ACOKBF,
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S2MPS11_IRQ_ACOKBR,
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S2MPS11_IRQ_PWRON1S,
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S2MPS11_IRQ_MRB,
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S2MPS11_IRQ_RTC60S,
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S2MPS11_IRQ_RTCA1,
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S2MPS11_IRQ_RTCA0,
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S2MPS11_IRQ_SMPL,
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S2MPS11_IRQ_RTC1S,
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S2MPS11_IRQ_WTSR,
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S2MPS11_IRQ_INT120C,
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S2MPS11_IRQ_INT140C,
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S2MPS11_IRQ_NR,
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};
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#define S2MPS11_IRQ_PWRONF_MASK (1 << 0)
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#define S2MPS11_IRQ_PWRONR_MASK (1 << 1)
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#define S2MPS11_IRQ_JIGONBF_MASK (1 << 2)
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#define S2MPS11_IRQ_JIGONBR_MASK (1 << 3)
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#define S2MPS11_IRQ_ACOKBF_MASK (1 << 4)
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#define S2MPS11_IRQ_ACOKBR_MASK (1 << 5)
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#define S2MPS11_IRQ_PWRON1S_MASK (1 << 6)
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#define S2MPS11_IRQ_MRB_MASK (1 << 7)
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#define S2MPS11_IRQ_RTC60S_MASK (1 << 0)
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#define S2MPS11_IRQ_RTCA1_MASK (1 << 1)
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#define S2MPS11_IRQ_RTCA0_MASK (1 << 2)
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#define S2MPS11_IRQ_SMPL_MASK (1 << 3)
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#define S2MPS11_IRQ_RTC1S_MASK (1 << 4)
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#define S2MPS11_IRQ_WTSR_MASK (1 << 5)
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#define S2MPS11_IRQ_INT120C_MASK (1 << 0)
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#define S2MPS11_IRQ_INT140C_MASK (1 << 1)
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enum s2mps14_irq {
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S2MPS14_IRQ_PWRONF,
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S2MPS14_IRQ_PWRONR,
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S2MPS14_IRQ_JIGONBF,
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S2MPS14_IRQ_JIGONBR,
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S2MPS14_IRQ_ACOKBF,
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S2MPS14_IRQ_ACOKBR,
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S2MPS14_IRQ_PWRON1S,
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S2MPS14_IRQ_MRB,
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S2MPS14_IRQ_RTC60S,
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S2MPS14_IRQ_RTCA1,
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S2MPS14_IRQ_RTCA0,
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S2MPS14_IRQ_SMPL,
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S2MPS14_IRQ_RTC1S,
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S2MPS14_IRQ_WTSR,
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S2MPS14_IRQ_INT120C,
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S2MPS14_IRQ_INT140C,
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S2MPS14_IRQ_TSD,
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S2MPS14_IRQ_NR,
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};
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enum s2mpu02_irq {
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S2MPU02_IRQ_PWRONF,
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S2MPU02_IRQ_PWRONR,
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S2MPU02_IRQ_JIGONBF,
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S2MPU02_IRQ_JIGONBR,
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S2MPU02_IRQ_ACOKBF,
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S2MPU02_IRQ_ACOKBR,
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S2MPU02_IRQ_PWRON1S,
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S2MPU02_IRQ_MRB,
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S2MPU02_IRQ_RTC60S,
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S2MPU02_IRQ_RTCA1,
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S2MPU02_IRQ_RTCA0,
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S2MPU02_IRQ_SMPL,
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S2MPU02_IRQ_RTC1S,
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S2MPU02_IRQ_WTSR,
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S2MPU02_IRQ_INT120C,
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S2MPU02_IRQ_INT140C,
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S2MPU02_IRQ_TSD,
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S2MPU02_IRQ_NR,
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};
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/* Masks for interrupts are the same as in s2mps11 */
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#define S2MPS14_IRQ_TSD_MASK (1 << 2)
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enum s5m8767_irq {
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S5M8767_IRQ_PWRR,
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S5M8767_IRQ_PWRF,
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S5M8767_IRQ_PWR1S,
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S5M8767_IRQ_JIGR,
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S5M8767_IRQ_JIGF,
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S5M8767_IRQ_LOWBAT2,
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S5M8767_IRQ_LOWBAT1,
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S5M8767_IRQ_MRB,
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S5M8767_IRQ_DVSOK2,
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S5M8767_IRQ_DVSOK3,
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S5M8767_IRQ_DVSOK4,
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S5M8767_IRQ_RTC60S,
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S5M8767_IRQ_RTCA1,
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S5M8767_IRQ_RTCA2,
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S5M8767_IRQ_SMPL,
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S5M8767_IRQ_RTC1S,
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S5M8767_IRQ_WTSR,
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S5M8767_IRQ_NR,
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};
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#define S5M8767_IRQ_PWRR_MASK (1 << 0)
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#define S5M8767_IRQ_PWRF_MASK (1 << 1)
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#define S5M8767_IRQ_PWR1S_MASK (1 << 3)
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#define S5M8767_IRQ_JIGR_MASK (1 << 4)
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#define S5M8767_IRQ_JIGF_MASK (1 << 5)
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#define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
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#define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
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#define S5M8767_IRQ_MRB_MASK (1 << 2)
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#define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
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#define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
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#define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
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#define S5M8767_IRQ_RTC60S_MASK (1 << 0)
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#define S5M8767_IRQ_RTCA1_MASK (1 << 1)
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#define S5M8767_IRQ_RTCA2_MASK (1 << 2)
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#define S5M8767_IRQ_SMPL_MASK (1 << 3)
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#define S5M8767_IRQ_RTC1S_MASK (1 << 4)
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#define S5M8767_IRQ_WTSR_MASK (1 << 5)
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#endif /* __LINUX_MFD_SEC_IRQ_H */
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133
linux-6.8.1/include/linux/mfd/samsung/rtc.h
Normal file
133
linux-6.8.1/include/linux/mfd/samsung/rtc.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2011-2014 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*/
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#ifndef __LINUX_MFD_SEC_RTC_H
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#define __LINUX_MFD_SEC_RTC_H
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enum s5m_rtc_reg {
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S5M_RTC_SEC,
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S5M_RTC_MIN,
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S5M_RTC_HOUR,
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S5M_RTC_WEEKDAY,
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S5M_RTC_DATE,
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S5M_RTC_MONTH,
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S5M_RTC_YEAR1,
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S5M_RTC_YEAR2,
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S5M_ALARM0_SEC,
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S5M_ALARM0_MIN,
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S5M_ALARM0_HOUR,
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S5M_ALARM0_WEEKDAY,
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S5M_ALARM0_DATE,
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S5M_ALARM0_MONTH,
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S5M_ALARM0_YEAR1,
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S5M_ALARM0_YEAR2,
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S5M_ALARM1_SEC,
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S5M_ALARM1_MIN,
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S5M_ALARM1_HOUR,
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S5M_ALARM1_WEEKDAY,
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S5M_ALARM1_DATE,
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S5M_ALARM1_MONTH,
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S5M_ALARM1_YEAR1,
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S5M_ALARM1_YEAR2,
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S5M_ALARM0_CONF,
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S5M_ALARM1_CONF,
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S5M_RTC_STATUS,
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S5M_WTSR_SMPL_CNTL,
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S5M_RTC_UDR_CON,
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S5M_RTC_REG_MAX,
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};
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enum s2mps_rtc_reg {
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S2MPS_RTC_CTRL,
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S2MPS_WTSR_SMPL_CNTL,
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S2MPS_RTC_UDR_CON,
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S2MPS_RSVD,
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S2MPS_RTC_SEC,
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S2MPS_RTC_MIN,
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S2MPS_RTC_HOUR,
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S2MPS_RTC_WEEKDAY,
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S2MPS_RTC_DATE,
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S2MPS_RTC_MONTH,
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S2MPS_RTC_YEAR,
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S2MPS_ALARM0_SEC,
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S2MPS_ALARM0_MIN,
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S2MPS_ALARM0_HOUR,
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S2MPS_ALARM0_WEEKDAY,
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S2MPS_ALARM0_DATE,
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S2MPS_ALARM0_MONTH,
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S2MPS_ALARM0_YEAR,
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S2MPS_ALARM1_SEC,
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S2MPS_ALARM1_MIN,
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S2MPS_ALARM1_HOUR,
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S2MPS_ALARM1_WEEKDAY,
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S2MPS_ALARM1_DATE,
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S2MPS_ALARM1_MONTH,
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S2MPS_ALARM1_YEAR,
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S2MPS_OFFSRC,
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S2MPS_RTC_REG_MAX,
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};
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#define RTC_I2C_ADDR (0x0C >> 1)
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#define HOUR_12 (1 << 7)
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#define HOUR_AMPM (1 << 6)
|
||||
#define HOUR_PM (1 << 5)
|
||||
#define S5M_ALARM0_STATUS (1 << 1)
|
||||
#define S5M_ALARM1_STATUS (1 << 2)
|
||||
#define S5M_UPDATE_AD (1 << 0)
|
||||
|
||||
#define S2MPS_ALARM0_STATUS (1 << 2)
|
||||
#define S2MPS_ALARM1_STATUS (1 << 1)
|
||||
|
||||
/* RTC Control Register */
|
||||
#define BCD_EN_SHIFT 0
|
||||
#define BCD_EN_MASK (1 << BCD_EN_SHIFT)
|
||||
#define MODEL24_SHIFT 1
|
||||
#define MODEL24_MASK (1 << MODEL24_SHIFT)
|
||||
/* RTC Update Register1 */
|
||||
#define S5M_RTC_UDR_SHIFT 0
|
||||
#define S5M_RTC_UDR_MASK (1 << S5M_RTC_UDR_SHIFT)
|
||||
#define S2MPS_RTC_WUDR_SHIFT 4
|
||||
#define S2MPS_RTC_WUDR_MASK (1 << S2MPS_RTC_WUDR_SHIFT)
|
||||
#define S2MPS15_RTC_AUDR_SHIFT 4
|
||||
#define S2MPS15_RTC_AUDR_MASK (1 << S2MPS15_RTC_AUDR_SHIFT)
|
||||
#define S2MPS13_RTC_AUDR_SHIFT 1
|
||||
#define S2MPS13_RTC_AUDR_MASK (1 << S2MPS13_RTC_AUDR_SHIFT)
|
||||
#define S2MPS15_RTC_WUDR_SHIFT 1
|
||||
#define S2MPS15_RTC_WUDR_MASK (1 << S2MPS15_RTC_WUDR_SHIFT)
|
||||
#define S2MPS_RTC_RUDR_SHIFT 0
|
||||
#define S2MPS_RTC_RUDR_MASK (1 << S2MPS_RTC_RUDR_SHIFT)
|
||||
#define RTC_TCON_SHIFT 1
|
||||
#define RTC_TCON_MASK (1 << RTC_TCON_SHIFT)
|
||||
#define S5M_RTC_TIME_EN_SHIFT 3
|
||||
#define S5M_RTC_TIME_EN_MASK (1 << S5M_RTC_TIME_EN_SHIFT)
|
||||
/*
|
||||
* UDR_T field in S5M_RTC_UDR_CON register determines the time needed
|
||||
* for updating alarm and time registers. Default is 7.32 ms.
|
||||
*/
|
||||
#define S5M_RTC_UDR_T_SHIFT 6
|
||||
#define S5M_RTC_UDR_T_MASK (0x3 << S5M_RTC_UDR_T_SHIFT)
|
||||
#define S5M_RTC_UDR_T_7320_US (0x0 << S5M_RTC_UDR_T_SHIFT)
|
||||
#define S5M_RTC_UDR_T_1830_US (0x1 << S5M_RTC_UDR_T_SHIFT)
|
||||
#define S5M_RTC_UDR_T_3660_US (0x2 << S5M_RTC_UDR_T_SHIFT)
|
||||
#define S5M_RTC_UDR_T_450_US (0x3 << S5M_RTC_UDR_T_SHIFT)
|
||||
|
||||
/* RTC Hour register */
|
||||
#define HOUR_PM_SHIFT 6
|
||||
#define HOUR_PM_MASK (1 << HOUR_PM_SHIFT)
|
||||
/* RTC Alarm Enable */
|
||||
#define ALARM_ENABLE_SHIFT 7
|
||||
#define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT)
|
||||
|
||||
#define SMPL_ENABLE_SHIFT 7
|
||||
#define SMPL_ENABLE_MASK (1 << SMPL_ENABLE_SHIFT)
|
||||
|
||||
#define WTSR_ENABLE_SHIFT 6
|
||||
#define WTSR_ENABLE_MASK (1 << WTSR_ENABLE_SHIFT)
|
||||
|
||||
#endif /* __LINUX_MFD_SEC_RTC_H */
|
||||
175
linux-6.8.1/include/linux/mfd/samsung/s2mpa01.h
Normal file
175
linux-6.8.1/include/linux/mfd/samsung/s2mpa01.h
Normal file
|
|
@ -0,0 +1,175 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd
|
||||
* http://www.samsung.com
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_S2MPA01_H
|
||||
#define __LINUX_MFD_S2MPA01_H
|
||||
|
||||
/* S2MPA01 registers */
|
||||
enum s2mpa01_reg {
|
||||
S2MPA01_REG_ID,
|
||||
S2MPA01_REG_INT1,
|
||||
S2MPA01_REG_INT2,
|
||||
S2MPA01_REG_INT3,
|
||||
S2MPA01_REG_INT1M,
|
||||
S2MPA01_REG_INT2M,
|
||||
S2MPA01_REG_INT3M,
|
||||
S2MPA01_REG_ST1,
|
||||
S2MPA01_REG_ST2,
|
||||
S2MPA01_REG_PWRONSRC,
|
||||
S2MPA01_REG_OFFSRC,
|
||||
S2MPA01_REG_RTC_BUF,
|
||||
S2MPA01_REG_CTRL1,
|
||||
S2MPA01_REG_ETC_TEST,
|
||||
S2MPA01_REG_RSVD1,
|
||||
S2MPA01_REG_BU_CHG,
|
||||
S2MPA01_REG_RAMP1,
|
||||
S2MPA01_REG_RAMP2,
|
||||
S2MPA01_REG_LDO_DSCH1,
|
||||
S2MPA01_REG_LDO_DSCH2,
|
||||
S2MPA01_REG_LDO_DSCH3,
|
||||
S2MPA01_REG_LDO_DSCH4,
|
||||
S2MPA01_REG_OTP_ADRL,
|
||||
S2MPA01_REG_OTP_ADRH,
|
||||
S2MPA01_REG_OTP_DATA,
|
||||
S2MPA01_REG_MON1SEL,
|
||||
S2MPA01_REG_MON2SEL,
|
||||
S2MPA01_REG_LEE,
|
||||
S2MPA01_REG_RSVD2,
|
||||
S2MPA01_REG_RSVD3,
|
||||
S2MPA01_REG_RSVD4,
|
||||
S2MPA01_REG_RSVD5,
|
||||
S2MPA01_REG_RSVD6,
|
||||
S2MPA01_REG_TOP_RSVD,
|
||||
S2MPA01_REG_DVS_SEL,
|
||||
S2MPA01_REG_DVS_PTR,
|
||||
S2MPA01_REG_DVS_DATA,
|
||||
S2MPA01_REG_RSVD_NO,
|
||||
S2MPA01_REG_UVLO,
|
||||
S2MPA01_REG_LEE_NO,
|
||||
S2MPA01_REG_B1CTRL1,
|
||||
S2MPA01_REG_B1CTRL2,
|
||||
S2MPA01_REG_B2CTRL1,
|
||||
S2MPA01_REG_B2CTRL2,
|
||||
S2MPA01_REG_B3CTRL1,
|
||||
S2MPA01_REG_B3CTRL2,
|
||||
S2MPA01_REG_B4CTRL1,
|
||||
S2MPA01_REG_B4CTRL2,
|
||||
S2MPA01_REG_B5CTRL1,
|
||||
S2MPA01_REG_B5CTRL2,
|
||||
S2MPA01_REG_B5CTRL3,
|
||||
S2MPA01_REG_B5CTRL4,
|
||||
S2MPA01_REG_B5CTRL5,
|
||||
S2MPA01_REG_B5CTRL6,
|
||||
S2MPA01_REG_B6CTRL1,
|
||||
S2MPA01_REG_B6CTRL2,
|
||||
S2MPA01_REG_B7CTRL1,
|
||||
S2MPA01_REG_B7CTRL2,
|
||||
S2MPA01_REG_B8CTRL1,
|
||||
S2MPA01_REG_B8CTRL2,
|
||||
S2MPA01_REG_B9CTRL1,
|
||||
S2MPA01_REG_B9CTRL2,
|
||||
S2MPA01_REG_B10CTRL1,
|
||||
S2MPA01_REG_B10CTRL2,
|
||||
S2MPA01_REG_L1CTRL,
|
||||
S2MPA01_REG_L2CTRL,
|
||||
S2MPA01_REG_L3CTRL,
|
||||
S2MPA01_REG_L4CTRL,
|
||||
S2MPA01_REG_L5CTRL,
|
||||
S2MPA01_REG_L6CTRL,
|
||||
S2MPA01_REG_L7CTRL,
|
||||
S2MPA01_REG_L8CTRL,
|
||||
S2MPA01_REG_L9CTRL,
|
||||
S2MPA01_REG_L10CTRL,
|
||||
S2MPA01_REG_L11CTRL,
|
||||
S2MPA01_REG_L12CTRL,
|
||||
S2MPA01_REG_L13CTRL,
|
||||
S2MPA01_REG_L14CTRL,
|
||||
S2MPA01_REG_L15CTRL,
|
||||
S2MPA01_REG_L16CTRL,
|
||||
S2MPA01_REG_L17CTRL,
|
||||
S2MPA01_REG_L18CTRL,
|
||||
S2MPA01_REG_L19CTRL,
|
||||
S2MPA01_REG_L20CTRL,
|
||||
S2MPA01_REG_L21CTRL,
|
||||
S2MPA01_REG_L22CTRL,
|
||||
S2MPA01_REG_L23CTRL,
|
||||
S2MPA01_REG_L24CTRL,
|
||||
S2MPA01_REG_L25CTRL,
|
||||
S2MPA01_REG_L26CTRL,
|
||||
|
||||
S2MPA01_REG_LDO_OVCB1,
|
||||
S2MPA01_REG_LDO_OVCB2,
|
||||
S2MPA01_REG_LDO_OVCB3,
|
||||
S2MPA01_REG_LDO_OVCB4,
|
||||
|
||||
};
|
||||
|
||||
/* S2MPA01 regulator ids */
|
||||
enum s2mpa01_regulators {
|
||||
S2MPA01_LDO1,
|
||||
S2MPA01_LDO2,
|
||||
S2MPA01_LDO3,
|
||||
S2MPA01_LDO4,
|
||||
S2MPA01_LDO5,
|
||||
S2MPA01_LDO6,
|
||||
S2MPA01_LDO7,
|
||||
S2MPA01_LDO8,
|
||||
S2MPA01_LDO9,
|
||||
S2MPA01_LDO10,
|
||||
S2MPA01_LDO11,
|
||||
S2MPA01_LDO12,
|
||||
S2MPA01_LDO13,
|
||||
S2MPA01_LDO14,
|
||||
S2MPA01_LDO15,
|
||||
S2MPA01_LDO16,
|
||||
S2MPA01_LDO17,
|
||||
S2MPA01_LDO18,
|
||||
S2MPA01_LDO19,
|
||||
S2MPA01_LDO20,
|
||||
S2MPA01_LDO21,
|
||||
S2MPA01_LDO22,
|
||||
S2MPA01_LDO23,
|
||||
S2MPA01_LDO24,
|
||||
S2MPA01_LDO25,
|
||||
S2MPA01_LDO26,
|
||||
|
||||
S2MPA01_BUCK1,
|
||||
S2MPA01_BUCK2,
|
||||
S2MPA01_BUCK3,
|
||||
S2MPA01_BUCK4,
|
||||
S2MPA01_BUCK5,
|
||||
S2MPA01_BUCK6,
|
||||
S2MPA01_BUCK7,
|
||||
S2MPA01_BUCK8,
|
||||
S2MPA01_BUCK9,
|
||||
S2MPA01_BUCK10,
|
||||
|
||||
S2MPA01_REGULATOR_MAX,
|
||||
};
|
||||
|
||||
#define S2MPA01_LDO_VSEL_MASK 0x3F
|
||||
#define S2MPA01_BUCK_VSEL_MASK 0xFF
|
||||
#define S2MPA01_ENABLE_MASK (0x03 << S2MPA01_ENABLE_SHIFT)
|
||||
#define S2MPA01_ENABLE_SHIFT 0x06
|
||||
#define S2MPA01_LDO_N_VOLTAGES (S2MPA01_LDO_VSEL_MASK + 1)
|
||||
#define S2MPA01_BUCK_N_VOLTAGES (S2MPA01_BUCK_VSEL_MASK + 1)
|
||||
|
||||
#define S2MPA01_RAMP_DELAY 12500 /* uV/us */
|
||||
|
||||
#define S2MPA01_BUCK16_RAMP_SHIFT 4
|
||||
#define S2MPA01_BUCK24_RAMP_SHIFT 6
|
||||
#define S2MPA01_BUCK3_RAMP_SHIFT 4
|
||||
#define S2MPA01_BUCK5_RAMP_SHIFT 6
|
||||
#define S2MPA01_BUCK7_RAMP_SHIFT 2
|
||||
#define S2MPA01_BUCK8910_RAMP_SHIFT 0
|
||||
|
||||
#define S2MPA01_BUCK1_RAMP_EN_SHIFT 3
|
||||
#define S2MPA01_BUCK2_RAMP_EN_SHIFT 2
|
||||
#define S2MPA01_BUCK3_RAMP_EN_SHIFT 1
|
||||
#define S2MPA01_BUCK4_RAMP_EN_SHIFT 0
|
||||
#define S2MPA01_PMIC_EN_SHIFT 6
|
||||
|
||||
#endif /*__LINUX_MFD_S2MPA01_H */
|
||||
198
linux-6.8.1/include/linux/mfd/samsung/s2mps11.h
Normal file
198
linux-6.8.1/include/linux/mfd/samsung/s2mps11.h
Normal file
|
|
@ -0,0 +1,198 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2012 Samsung Electronics Co., Ltd
|
||||
* http://www.samsung.com
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_S2MPS11_H
|
||||
#define __LINUX_MFD_S2MPS11_H
|
||||
|
||||
/* S2MPS11 registers */
|
||||
enum s2mps11_reg {
|
||||
S2MPS11_REG_ID,
|
||||
S2MPS11_REG_INT1,
|
||||
S2MPS11_REG_INT2,
|
||||
S2MPS11_REG_INT3,
|
||||
S2MPS11_REG_INT1M,
|
||||
S2MPS11_REG_INT2M,
|
||||
S2MPS11_REG_INT3M,
|
||||
S2MPS11_REG_ST1,
|
||||
S2MPS11_REG_ST2,
|
||||
S2MPS11_REG_OFFSRC,
|
||||
S2MPS11_REG_PWRONSRC,
|
||||
S2MPS11_REG_RTC_CTRL,
|
||||
S2MPS11_REG_CTRL1,
|
||||
S2MPS11_REG_ETC_TEST,
|
||||
S2MPS11_REG_RSVD3,
|
||||
S2MPS11_REG_BU_CHG,
|
||||
S2MPS11_REG_RAMP,
|
||||
S2MPS11_REG_RAMP_BUCK,
|
||||
S2MPS11_REG_LDO1_8,
|
||||
S2MPS11_REG_LDO9_16,
|
||||
S2MPS11_REG_LDO17_24,
|
||||
S2MPS11_REG_LDO25_32,
|
||||
S2MPS11_REG_LDO33_38,
|
||||
S2MPS11_REG_LDO1_8_1,
|
||||
S2MPS11_REG_LDO9_16_1,
|
||||
S2MPS11_REG_LDO17_24_1,
|
||||
S2MPS11_REG_LDO25_32_1,
|
||||
S2MPS11_REG_LDO33_38_1,
|
||||
S2MPS11_REG_OTP_ADRL,
|
||||
S2MPS11_REG_OTP_ADRH,
|
||||
S2MPS11_REG_OTP_DATA,
|
||||
S2MPS11_REG_MON1SEL,
|
||||
S2MPS11_REG_MON2SEL,
|
||||
S2MPS11_REG_LEE,
|
||||
S2MPS11_REG_RSVD_NO,
|
||||
S2MPS11_REG_UVLO,
|
||||
S2MPS11_REG_LEE_NO,
|
||||
S2MPS11_REG_B1CTRL1,
|
||||
S2MPS11_REG_B1CTRL2,
|
||||
S2MPS11_REG_B2CTRL1,
|
||||
S2MPS11_REG_B2CTRL2,
|
||||
S2MPS11_REG_B3CTRL1,
|
||||
S2MPS11_REG_B3CTRL2,
|
||||
S2MPS11_REG_B4CTRL1,
|
||||
S2MPS11_REG_B4CTRL2,
|
||||
S2MPS11_REG_B5CTRL1,
|
||||
S2MPS11_REG_BUCK5_SW,
|
||||
S2MPS11_REG_B5CTRL2,
|
||||
S2MPS11_REG_B5CTRL3,
|
||||
S2MPS11_REG_B5CTRL4,
|
||||
S2MPS11_REG_B5CTRL5,
|
||||
S2MPS11_REG_B6CTRL1,
|
||||
S2MPS11_REG_B6CTRL2,
|
||||
S2MPS11_REG_B7CTRL1,
|
||||
S2MPS11_REG_B7CTRL2,
|
||||
S2MPS11_REG_B8CTRL1,
|
||||
S2MPS11_REG_B8CTRL2,
|
||||
S2MPS11_REG_B9CTRL1,
|
||||
S2MPS11_REG_B9CTRL2,
|
||||
S2MPS11_REG_B10CTRL1,
|
||||
S2MPS11_REG_B10CTRL2,
|
||||
S2MPS11_REG_L1CTRL,
|
||||
S2MPS11_REG_L2CTRL,
|
||||
S2MPS11_REG_L3CTRL,
|
||||
S2MPS11_REG_L4CTRL,
|
||||
S2MPS11_REG_L5CTRL,
|
||||
S2MPS11_REG_L6CTRL,
|
||||
S2MPS11_REG_L7CTRL,
|
||||
S2MPS11_REG_L8CTRL,
|
||||
S2MPS11_REG_L9CTRL,
|
||||
S2MPS11_REG_L10CTRL,
|
||||
S2MPS11_REG_L11CTRL,
|
||||
S2MPS11_REG_L12CTRL,
|
||||
S2MPS11_REG_L13CTRL,
|
||||
S2MPS11_REG_L14CTRL,
|
||||
S2MPS11_REG_L15CTRL,
|
||||
S2MPS11_REG_L16CTRL,
|
||||
S2MPS11_REG_L17CTRL,
|
||||
S2MPS11_REG_L18CTRL,
|
||||
S2MPS11_REG_L19CTRL,
|
||||
S2MPS11_REG_L20CTRL,
|
||||
S2MPS11_REG_L21CTRL,
|
||||
S2MPS11_REG_L22CTRL,
|
||||
S2MPS11_REG_L23CTRL,
|
||||
S2MPS11_REG_L24CTRL,
|
||||
S2MPS11_REG_L25CTRL,
|
||||
S2MPS11_REG_L26CTRL,
|
||||
S2MPS11_REG_L27CTRL,
|
||||
S2MPS11_REG_L28CTRL,
|
||||
S2MPS11_REG_L29CTRL,
|
||||
S2MPS11_REG_L30CTRL,
|
||||
S2MPS11_REG_L31CTRL,
|
||||
S2MPS11_REG_L32CTRL,
|
||||
S2MPS11_REG_L33CTRL,
|
||||
S2MPS11_REG_L34CTRL,
|
||||
S2MPS11_REG_L35CTRL,
|
||||
S2MPS11_REG_L36CTRL,
|
||||
S2MPS11_REG_L37CTRL,
|
||||
S2MPS11_REG_L38CTRL,
|
||||
};
|
||||
|
||||
/* S2MPS11 regulator ids */
|
||||
enum s2mps11_regulators {
|
||||
S2MPS11_LDO1,
|
||||
S2MPS11_LDO2,
|
||||
S2MPS11_LDO3,
|
||||
S2MPS11_LDO4,
|
||||
S2MPS11_LDO5,
|
||||
S2MPS11_LDO6,
|
||||
S2MPS11_LDO7,
|
||||
S2MPS11_LDO8,
|
||||
S2MPS11_LDO9,
|
||||
S2MPS11_LDO10,
|
||||
S2MPS11_LDO11,
|
||||
S2MPS11_LDO12,
|
||||
S2MPS11_LDO13,
|
||||
S2MPS11_LDO14,
|
||||
S2MPS11_LDO15,
|
||||
S2MPS11_LDO16,
|
||||
S2MPS11_LDO17,
|
||||
S2MPS11_LDO18,
|
||||
S2MPS11_LDO19,
|
||||
S2MPS11_LDO20,
|
||||
S2MPS11_LDO21,
|
||||
S2MPS11_LDO22,
|
||||
S2MPS11_LDO23,
|
||||
S2MPS11_LDO24,
|
||||
S2MPS11_LDO25,
|
||||
S2MPS11_LDO26,
|
||||
S2MPS11_LDO27,
|
||||
S2MPS11_LDO28,
|
||||
S2MPS11_LDO29,
|
||||
S2MPS11_LDO30,
|
||||
S2MPS11_LDO31,
|
||||
S2MPS11_LDO32,
|
||||
S2MPS11_LDO33,
|
||||
S2MPS11_LDO34,
|
||||
S2MPS11_LDO35,
|
||||
S2MPS11_LDO36,
|
||||
S2MPS11_LDO37,
|
||||
S2MPS11_LDO38,
|
||||
S2MPS11_BUCK1,
|
||||
S2MPS11_BUCK2,
|
||||
S2MPS11_BUCK3,
|
||||
S2MPS11_BUCK4,
|
||||
S2MPS11_BUCK5,
|
||||
S2MPS11_BUCK6,
|
||||
S2MPS11_BUCK7,
|
||||
S2MPS11_BUCK8,
|
||||
S2MPS11_BUCK9,
|
||||
S2MPS11_BUCK10,
|
||||
|
||||
S2MPS11_REGULATOR_MAX,
|
||||
};
|
||||
|
||||
#define S2MPS11_LDO_VSEL_MASK 0x3F
|
||||
#define S2MPS11_BUCK_VSEL_MASK 0xFF
|
||||
#define S2MPS11_BUCK9_VSEL_MASK 0x1F
|
||||
#define S2MPS11_ENABLE_MASK (0x03 << S2MPS11_ENABLE_SHIFT)
|
||||
#define S2MPS11_ENABLE_SHIFT 0x06
|
||||
#define S2MPS11_LDO_N_VOLTAGES (S2MPS11_LDO_VSEL_MASK + 1)
|
||||
#define S2MPS11_BUCK12346_N_VOLTAGES 153
|
||||
#define S2MPS11_BUCK5_N_VOLTAGES 216
|
||||
#define S2MPS11_BUCK7810_N_VOLTAGES 225
|
||||
#define S2MPS11_BUCK9_N_VOLTAGES (S2MPS11_BUCK9_VSEL_MASK + 1)
|
||||
#define S2MPS11_RAMP_DELAY 25000 /* uV/us */
|
||||
|
||||
#define S2MPS11_CTRL1_PWRHOLD_MASK BIT(4)
|
||||
|
||||
#define S2MPS11_BUCK2_RAMP_SHIFT 6
|
||||
#define S2MPS11_BUCK34_RAMP_SHIFT 4
|
||||
#define S2MPS11_BUCK5_RAMP_SHIFT 6
|
||||
#define S2MPS11_BUCK16_RAMP_SHIFT 4
|
||||
#define S2MPS11_BUCK7810_RAMP_SHIFT 2
|
||||
#define S2MPS11_BUCK9_RAMP_SHIFT 0
|
||||
#define S2MPS11_BUCK2_RAMP_EN_SHIFT 3
|
||||
#define S2MPS11_BUCK3_RAMP_EN_SHIFT 2
|
||||
#define S2MPS11_BUCK4_RAMP_EN_SHIFT 1
|
||||
#define S2MPS11_BUCK6_RAMP_EN_SHIFT 0
|
||||
#define S2MPS11_PMIC_EN_SHIFT 6
|
||||
|
||||
/*
|
||||
* Bits for "enable suspend" (On/Off controlled by PWREN)
|
||||
* are the same as in S2MPS14: S2MPS14_ENABLE_SUSPEND
|
||||
*/
|
||||
|
||||
#endif /* __LINUX_MFD_S2MPS11_H */
|
||||
177
linux-6.8.1/include/linux/mfd/samsung/s2mps13.h
Normal file
177
linux-6.8.1/include/linux/mfd/samsung/s2mps13.h
Normal file
|
|
@ -0,0 +1,177 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd
|
||||
* http://www.samsung.com
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_S2MPS13_H
|
||||
#define __LINUX_MFD_S2MPS13_H
|
||||
|
||||
/* S2MPS13 registers */
|
||||
enum s2mps13_reg {
|
||||
S2MPS13_REG_ID,
|
||||
S2MPS13_REG_INT1,
|
||||
S2MPS13_REG_INT2,
|
||||
S2MPS13_REG_INT3,
|
||||
S2MPS13_REG_INT1M,
|
||||
S2MPS13_REG_INT2M,
|
||||
S2MPS13_REG_INT3M,
|
||||
S2MPS13_REG_ST1,
|
||||
S2MPS13_REG_ST2,
|
||||
S2MPS13_REG_PWRONSRC,
|
||||
S2MPS13_REG_OFFSRC,
|
||||
S2MPS13_REG_BU_CHG,
|
||||
S2MPS13_REG_RTCCTRL,
|
||||
S2MPS13_REG_CTRL1,
|
||||
S2MPS13_REG_CTRL2,
|
||||
S2MPS13_REG_RSVD1,
|
||||
S2MPS13_REG_RSVD2,
|
||||
S2MPS13_REG_RSVD3,
|
||||
S2MPS13_REG_RSVD4,
|
||||
S2MPS13_REG_RSVD5,
|
||||
S2MPS13_REG_RSVD6,
|
||||
S2MPS13_REG_CTRL3,
|
||||
S2MPS13_REG_RSVD7,
|
||||
S2MPS13_REG_RSVD8,
|
||||
S2MPS13_REG_WRSTBI,
|
||||
S2MPS13_REG_B1CTRL,
|
||||
S2MPS13_REG_B1OUT,
|
||||
S2MPS13_REG_B2CTRL,
|
||||
S2MPS13_REG_B2OUT,
|
||||
S2MPS13_REG_B3CTRL,
|
||||
S2MPS13_REG_B3OUT,
|
||||
S2MPS13_REG_B4CTRL,
|
||||
S2MPS13_REG_B4OUT,
|
||||
S2MPS13_REG_B5CTRL,
|
||||
S2MPS13_REG_B5OUT,
|
||||
S2MPS13_REG_B6CTRL,
|
||||
S2MPS13_REG_B6OUT,
|
||||
S2MPS13_REG_B7CTRL,
|
||||
S2MPS13_REG_B7SW,
|
||||
S2MPS13_REG_B7OUT,
|
||||
S2MPS13_REG_B8CTRL,
|
||||
S2MPS13_REG_B8OUT,
|
||||
S2MPS13_REG_B9CTRL,
|
||||
S2MPS13_REG_B9OUT,
|
||||
S2MPS13_REG_B10CTRL,
|
||||
S2MPS13_REG_B10OUT,
|
||||
S2MPS13_REG_BB1CTRL,
|
||||
S2MPS13_REG_BB1OUT,
|
||||
S2MPS13_REG_BUCK_RAMP1,
|
||||
S2MPS13_REG_BUCK_RAMP2,
|
||||
S2MPS13_REG_LDO_DVS1,
|
||||
S2MPS13_REG_LDO_DVS2,
|
||||
S2MPS13_REG_LDO_DVS3,
|
||||
S2MPS13_REG_B6OUT2,
|
||||
S2MPS13_REG_L1CTRL,
|
||||
S2MPS13_REG_L2CTRL,
|
||||
S2MPS13_REG_L3CTRL,
|
||||
S2MPS13_REG_L4CTRL,
|
||||
S2MPS13_REG_L5CTRL,
|
||||
S2MPS13_REG_L6CTRL,
|
||||
S2MPS13_REG_L7CTRL,
|
||||
S2MPS13_REG_L8CTRL,
|
||||
S2MPS13_REG_L9CTRL,
|
||||
S2MPS13_REG_L10CTRL,
|
||||
S2MPS13_REG_L11CTRL,
|
||||
S2MPS13_REG_L12CTRL,
|
||||
S2MPS13_REG_L13CTRL,
|
||||
S2MPS13_REG_L14CTRL,
|
||||
S2MPS13_REG_L15CTRL,
|
||||
S2MPS13_REG_L16CTRL,
|
||||
S2MPS13_REG_L17CTRL,
|
||||
S2MPS13_REG_L18CTRL,
|
||||
S2MPS13_REG_L19CTRL,
|
||||
S2MPS13_REG_L20CTRL,
|
||||
S2MPS13_REG_L21CTRL,
|
||||
S2MPS13_REG_L22CTRL,
|
||||
S2MPS13_REG_L23CTRL,
|
||||
S2MPS13_REG_L24CTRL,
|
||||
S2MPS13_REG_L25CTRL,
|
||||
S2MPS13_REG_L26CTRL,
|
||||
S2MPS13_REG_L27CTRL,
|
||||
S2MPS13_REG_L28CTRL,
|
||||
S2MPS13_REG_L29CTRL,
|
||||
S2MPS13_REG_L30CTRL,
|
||||
S2MPS13_REG_L31CTRL,
|
||||
S2MPS13_REG_L32CTRL,
|
||||
S2MPS13_REG_L33CTRL,
|
||||
S2MPS13_REG_L34CTRL,
|
||||
S2MPS13_REG_L35CTRL,
|
||||
S2MPS13_REG_L36CTRL,
|
||||
S2MPS13_REG_L37CTRL,
|
||||
S2MPS13_REG_L38CTRL,
|
||||
S2MPS13_REG_L39CTRL,
|
||||
S2MPS13_REG_L40CTRL,
|
||||
S2MPS13_REG_LDODSCH1,
|
||||
S2MPS13_REG_LDODSCH2,
|
||||
S2MPS13_REG_LDODSCH3,
|
||||
S2MPS13_REG_LDODSCH4,
|
||||
S2MPS13_REG_LDODSCH5,
|
||||
};
|
||||
|
||||
/* regulator ids */
|
||||
enum s2mps13_regulators {
|
||||
S2MPS13_LDO1,
|
||||
S2MPS13_LDO2,
|
||||
S2MPS13_LDO3,
|
||||
S2MPS13_LDO4,
|
||||
S2MPS13_LDO5,
|
||||
S2MPS13_LDO6,
|
||||
S2MPS13_LDO7,
|
||||
S2MPS13_LDO8,
|
||||
S2MPS13_LDO9,
|
||||
S2MPS13_LDO10,
|
||||
S2MPS13_LDO11,
|
||||
S2MPS13_LDO12,
|
||||
S2MPS13_LDO13,
|
||||
S2MPS13_LDO14,
|
||||
S2MPS13_LDO15,
|
||||
S2MPS13_LDO16,
|
||||
S2MPS13_LDO17,
|
||||
S2MPS13_LDO18,
|
||||
S2MPS13_LDO19,
|
||||
S2MPS13_LDO20,
|
||||
S2MPS13_LDO21,
|
||||
S2MPS13_LDO22,
|
||||
S2MPS13_LDO23,
|
||||
S2MPS13_LDO24,
|
||||
S2MPS13_LDO25,
|
||||
S2MPS13_LDO26,
|
||||
S2MPS13_LDO27,
|
||||
S2MPS13_LDO28,
|
||||
S2MPS13_LDO29,
|
||||
S2MPS13_LDO30,
|
||||
S2MPS13_LDO31,
|
||||
S2MPS13_LDO32,
|
||||
S2MPS13_LDO33,
|
||||
S2MPS13_LDO34,
|
||||
S2MPS13_LDO35,
|
||||
S2MPS13_LDO36,
|
||||
S2MPS13_LDO37,
|
||||
S2MPS13_LDO38,
|
||||
S2MPS13_LDO39,
|
||||
S2MPS13_LDO40,
|
||||
S2MPS13_BUCK1,
|
||||
S2MPS13_BUCK2,
|
||||
S2MPS13_BUCK3,
|
||||
S2MPS13_BUCK4,
|
||||
S2MPS13_BUCK5,
|
||||
S2MPS13_BUCK6,
|
||||
S2MPS13_BUCK7,
|
||||
S2MPS13_BUCK8,
|
||||
S2MPS13_BUCK9,
|
||||
S2MPS13_BUCK10,
|
||||
|
||||
S2MPS13_REGULATOR_MAX,
|
||||
};
|
||||
|
||||
/*
|
||||
* Default ramp delay in uv/us. Datasheet says that ramp delay can be
|
||||
* controlled however it does not specify which register is used for that.
|
||||
* Let's assume that default value will be set.
|
||||
*/
|
||||
#define S2MPS13_BUCK_RAMP_DELAY 12500
|
||||
#define S2MPS13_REG_WRSTBI_MASK BIT(5)
|
||||
|
||||
#endif /* __LINUX_MFD_S2MPS13_H */
|
||||
134
linux-6.8.1/include/linux/mfd/samsung/s2mps14.h
Normal file
134
linux-6.8.1/include/linux/mfd/samsung/s2mps14.h
Normal file
|
|
@ -0,0 +1,134 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd
|
||||
* http://www.samsung.com
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_S2MPS14_H
|
||||
#define __LINUX_MFD_S2MPS14_H
|
||||
|
||||
/* S2MPS14 registers */
|
||||
enum s2mps14_reg {
|
||||
S2MPS14_REG_ID,
|
||||
S2MPS14_REG_INT1,
|
||||
S2MPS14_REG_INT2,
|
||||
S2MPS14_REG_INT3,
|
||||
S2MPS14_REG_INT1M,
|
||||
S2MPS14_REG_INT2M,
|
||||
S2MPS14_REG_INT3M,
|
||||
S2MPS14_REG_ST1,
|
||||
S2MPS14_REG_ST2,
|
||||
S2MPS14_REG_PWRONSRC,
|
||||
S2MPS14_REG_OFFSRC,
|
||||
S2MPS14_REG_BU_CHG,
|
||||
S2MPS14_REG_RTCCTRL,
|
||||
S2MPS14_REG_CTRL1,
|
||||
S2MPS14_REG_CTRL2,
|
||||
S2MPS14_REG_RSVD1,
|
||||
S2MPS14_REG_RSVD2,
|
||||
S2MPS14_REG_RSVD3,
|
||||
S2MPS14_REG_RSVD4,
|
||||
S2MPS14_REG_RSVD5,
|
||||
S2MPS14_REG_RSVD6,
|
||||
S2MPS14_REG_CTRL3,
|
||||
S2MPS14_REG_RSVD7,
|
||||
S2MPS14_REG_RSVD8,
|
||||
S2MPS14_REG_WRSTBI,
|
||||
S2MPS14_REG_B1CTRL1,
|
||||
S2MPS14_REG_B1CTRL2,
|
||||
S2MPS14_REG_B2CTRL1,
|
||||
S2MPS14_REG_B2CTRL2,
|
||||
S2MPS14_REG_B3CTRL1,
|
||||
S2MPS14_REG_B3CTRL2,
|
||||
S2MPS14_REG_B4CTRL1,
|
||||
S2MPS14_REG_B4CTRL2,
|
||||
S2MPS14_REG_B5CTRL1,
|
||||
S2MPS14_REG_B5CTRL2,
|
||||
S2MPS14_REG_L1CTRL,
|
||||
S2MPS14_REG_L2CTRL,
|
||||
S2MPS14_REG_L3CTRL,
|
||||
S2MPS14_REG_L4CTRL,
|
||||
S2MPS14_REG_L5CTRL,
|
||||
S2MPS14_REG_L6CTRL,
|
||||
S2MPS14_REG_L7CTRL,
|
||||
S2MPS14_REG_L8CTRL,
|
||||
S2MPS14_REG_L9CTRL,
|
||||
S2MPS14_REG_L10CTRL,
|
||||
S2MPS14_REG_L11CTRL,
|
||||
S2MPS14_REG_L12CTRL,
|
||||
S2MPS14_REG_L13CTRL,
|
||||
S2MPS14_REG_L14CTRL,
|
||||
S2MPS14_REG_L15CTRL,
|
||||
S2MPS14_REG_L16CTRL,
|
||||
S2MPS14_REG_L17CTRL,
|
||||
S2MPS14_REG_L18CTRL,
|
||||
S2MPS14_REG_L19CTRL,
|
||||
S2MPS14_REG_L20CTRL,
|
||||
S2MPS14_REG_L21CTRL,
|
||||
S2MPS14_REG_L22CTRL,
|
||||
S2MPS14_REG_L23CTRL,
|
||||
S2MPS14_REG_L24CTRL,
|
||||
S2MPS14_REG_L25CTRL,
|
||||
S2MPS14_REG_LDODSCH1,
|
||||
S2MPS14_REG_LDODSCH2,
|
||||
S2MPS14_REG_LDODSCH3,
|
||||
};
|
||||
|
||||
/* S2MPS14 regulator ids */
|
||||
enum s2mps14_regulators {
|
||||
S2MPS14_LDO1,
|
||||
S2MPS14_LDO2,
|
||||
S2MPS14_LDO3,
|
||||
S2MPS14_LDO4,
|
||||
S2MPS14_LDO5,
|
||||
S2MPS14_LDO6,
|
||||
S2MPS14_LDO7,
|
||||
S2MPS14_LDO8,
|
||||
S2MPS14_LDO9,
|
||||
S2MPS14_LDO10,
|
||||
S2MPS14_LDO11,
|
||||
S2MPS14_LDO12,
|
||||
S2MPS14_LDO13,
|
||||
S2MPS14_LDO14,
|
||||
S2MPS14_LDO15,
|
||||
S2MPS14_LDO16,
|
||||
S2MPS14_LDO17,
|
||||
S2MPS14_LDO18,
|
||||
S2MPS14_LDO19,
|
||||
S2MPS14_LDO20,
|
||||
S2MPS14_LDO21,
|
||||
S2MPS14_LDO22,
|
||||
S2MPS14_LDO23,
|
||||
S2MPS14_LDO24,
|
||||
S2MPS14_LDO25,
|
||||
S2MPS14_BUCK1,
|
||||
S2MPS14_BUCK2,
|
||||
S2MPS14_BUCK3,
|
||||
S2MPS14_BUCK4,
|
||||
S2MPS14_BUCK5,
|
||||
|
||||
S2MPS14_REGULATOR_MAX,
|
||||
};
|
||||
|
||||
/* Regulator constraints for BUCKx */
|
||||
#define S2MPS14_BUCK1235_START_SEL 0x20
|
||||
#define S2MPS14_BUCK4_START_SEL 0x40
|
||||
/*
|
||||
* Default ramp delay in uv/us. Datasheet says that ramp delay can be
|
||||
* controlled however it does not specify which register is used for that.
|
||||
* Let's assume that default value will be set.
|
||||
*/
|
||||
#define S2MPS14_BUCK_RAMP_DELAY 12500
|
||||
|
||||
#define S2MPS14_LDO_VSEL_MASK 0x3F
|
||||
#define S2MPS14_BUCK_VSEL_MASK 0xFF
|
||||
#define S2MPS14_ENABLE_MASK (0x03 << S2MPS14_ENABLE_SHIFT)
|
||||
#define S2MPS14_ENABLE_SHIFT 6
|
||||
/* On/Off controlled by PWREN */
|
||||
#define S2MPS14_ENABLE_SUSPEND (0x01 << S2MPS14_ENABLE_SHIFT)
|
||||
/* On/Off controlled by LDO10EN or EMMCEN */
|
||||
#define S2MPS14_ENABLE_EXT_CONTROL (0x00 << S2MPS14_ENABLE_SHIFT)
|
||||
#define S2MPS14_LDO_N_VOLTAGES (S2MPS14_LDO_VSEL_MASK + 1)
|
||||
#define S2MPS14_BUCK_N_VOLTAGES (S2MPS14_BUCK_VSEL_MASK + 1)
|
||||
|
||||
#endif /* __LINUX_MFD_S2MPS14_H */
|
||||
149
linux-6.8.1/include/linux/mfd/samsung/s2mps15.h
Normal file
149
linux-6.8.1/include/linux/mfd/samsung/s2mps15.h
Normal file
|
|
@ -0,0 +1,149 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2015 Samsung Electronics Co., Ltd
|
||||
* http://www.samsung.com
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_S2MPS15_H
|
||||
#define __LINUX_MFD_S2MPS15_H
|
||||
|
||||
/* S2MPS15 registers */
|
||||
enum s2mps15_reg {
|
||||
S2MPS15_REG_ID,
|
||||
S2MPS15_REG_INT1,
|
||||
S2MPS15_REG_INT2,
|
||||
S2MPS15_REG_INT3,
|
||||
S2MPS15_REG_INT1M,
|
||||
S2MPS15_REG_INT2M,
|
||||
S2MPS15_REG_INT3M,
|
||||
S2MPS15_REG_ST1,
|
||||
S2MPS15_REG_ST2,
|
||||
S2MPS15_REG_PWRONSRC,
|
||||
S2MPS15_REG_OFFSRC,
|
||||
S2MPS15_REG_BU_CHG,
|
||||
S2MPS15_REG_RTC_BUF,
|
||||
S2MPS15_REG_CTRL1,
|
||||
S2MPS15_REG_CTRL2,
|
||||
S2MPS15_REG_RSVD1,
|
||||
S2MPS15_REG_RSVD2,
|
||||
S2MPS15_REG_RSVD3,
|
||||
S2MPS15_REG_RSVD4,
|
||||
S2MPS15_REG_RSVD5,
|
||||
S2MPS15_REG_RSVD6,
|
||||
S2MPS15_REG_CTRL3,
|
||||
S2MPS15_REG_RSVD7,
|
||||
S2MPS15_REG_RSVD8,
|
||||
S2MPS15_REG_RSVD9,
|
||||
S2MPS15_REG_B1CTRL1,
|
||||
S2MPS15_REG_B1CTRL2,
|
||||
S2MPS15_REG_B2CTRL1,
|
||||
S2MPS15_REG_B2CTRL2,
|
||||
S2MPS15_REG_B3CTRL1,
|
||||
S2MPS15_REG_B3CTRL2,
|
||||
S2MPS15_REG_B4CTRL1,
|
||||
S2MPS15_REG_B4CTRL2,
|
||||
S2MPS15_REG_B5CTRL1,
|
||||
S2MPS15_REG_B5CTRL2,
|
||||
S2MPS15_REG_B6CTRL1,
|
||||
S2MPS15_REG_B6CTRL2,
|
||||
S2MPS15_REG_B7CTRL1,
|
||||
S2MPS15_REG_B7CTRL2,
|
||||
S2MPS15_REG_B8CTRL1,
|
||||
S2MPS15_REG_B8CTRL2,
|
||||
S2MPS15_REG_B9CTRL1,
|
||||
S2MPS15_REG_B9CTRL2,
|
||||
S2MPS15_REG_B10CTRL1,
|
||||
S2MPS15_REG_B10CTRL2,
|
||||
S2MPS15_REG_BBCTRL1,
|
||||
S2MPS15_REG_BBCTRL2,
|
||||
S2MPS15_REG_BRAMP,
|
||||
S2MPS15_REG_LDODVS1,
|
||||
S2MPS15_REG_LDODVS2,
|
||||
S2MPS15_REG_LDODVS3,
|
||||
S2MPS15_REG_LDODVS4,
|
||||
S2MPS15_REG_L1CTRL,
|
||||
S2MPS15_REG_L2CTRL,
|
||||
S2MPS15_REG_L3CTRL,
|
||||
S2MPS15_REG_L4CTRL,
|
||||
S2MPS15_REG_L5CTRL,
|
||||
S2MPS15_REG_L6CTRL,
|
||||
S2MPS15_REG_L7CTRL,
|
||||
S2MPS15_REG_L8CTRL,
|
||||
S2MPS15_REG_L9CTRL,
|
||||
S2MPS15_REG_L10CTRL,
|
||||
S2MPS15_REG_L11CTRL,
|
||||
S2MPS15_REG_L12CTRL,
|
||||
S2MPS15_REG_L13CTRL,
|
||||
S2MPS15_REG_L14CTRL,
|
||||
S2MPS15_REG_L15CTRL,
|
||||
S2MPS15_REG_L16CTRL,
|
||||
S2MPS15_REG_L17CTRL,
|
||||
S2MPS15_REG_L18CTRL,
|
||||
S2MPS15_REG_L19CTRL,
|
||||
S2MPS15_REG_L20CTRL,
|
||||
S2MPS15_REG_L21CTRL,
|
||||
S2MPS15_REG_L22CTRL,
|
||||
S2MPS15_REG_L23CTRL,
|
||||
S2MPS15_REG_L24CTRL,
|
||||
S2MPS15_REG_L25CTRL,
|
||||
S2MPS15_REG_L26CTRL,
|
||||
S2MPS15_REG_L27CTRL,
|
||||
S2MPS15_REG_LDODSCH1,
|
||||
S2MPS15_REG_LDODSCH2,
|
||||
S2MPS15_REG_LDODSCH3,
|
||||
S2MPS15_REG_LDODSCH4,
|
||||
};
|
||||
|
||||
/* S2MPS15 regulator ids */
|
||||
enum s2mps15_regulators {
|
||||
S2MPS15_LDO1,
|
||||
S2MPS15_LDO2,
|
||||
S2MPS15_LDO3,
|
||||
S2MPS15_LDO4,
|
||||
S2MPS15_LDO5,
|
||||
S2MPS15_LDO6,
|
||||
S2MPS15_LDO7,
|
||||
S2MPS15_LDO8,
|
||||
S2MPS15_LDO9,
|
||||
S2MPS15_LDO10,
|
||||
S2MPS15_LDO11,
|
||||
S2MPS15_LDO12,
|
||||
S2MPS15_LDO13,
|
||||
S2MPS15_LDO14,
|
||||
S2MPS15_LDO15,
|
||||
S2MPS15_LDO16,
|
||||
S2MPS15_LDO17,
|
||||
S2MPS15_LDO18,
|
||||
S2MPS15_LDO19,
|
||||
S2MPS15_LDO20,
|
||||
S2MPS15_LDO21,
|
||||
S2MPS15_LDO22,
|
||||
S2MPS15_LDO23,
|
||||
S2MPS15_LDO24,
|
||||
S2MPS15_LDO25,
|
||||
S2MPS15_LDO26,
|
||||
S2MPS15_LDO27,
|
||||
S2MPS15_BUCK1,
|
||||
S2MPS15_BUCK2,
|
||||
S2MPS15_BUCK3,
|
||||
S2MPS15_BUCK4,
|
||||
S2MPS15_BUCK5,
|
||||
S2MPS15_BUCK6,
|
||||
S2MPS15_BUCK7,
|
||||
S2MPS15_BUCK8,
|
||||
S2MPS15_BUCK9,
|
||||
S2MPS15_BUCK10,
|
||||
S2MPS15_BUCK11,
|
||||
S2MPS15_REGULATOR_MAX,
|
||||
};
|
||||
|
||||
#define S2MPS15_LDO_VSEL_MASK (0x3F)
|
||||
#define S2MPS15_BUCK_VSEL_MASK (0xFF)
|
||||
|
||||
#define S2MPS15_ENABLE_SHIFT (0x06)
|
||||
#define S2MPS15_ENABLE_MASK (0x03 << S2MPS15_ENABLE_SHIFT)
|
||||
|
||||
#define S2MPS15_LDO_N_VOLTAGES (S2MPS15_LDO_VSEL_MASK + 1)
|
||||
#define S2MPS15_BUCK_N_VOLTAGES (S2MPS15_BUCK_VSEL_MASK + 1)
|
||||
|
||||
#endif /* __LINUX_MFD_S2MPS15_H */
|
||||
189
linux-6.8.1/include/linux/mfd/samsung/s2mpu02.h
Normal file
189
linux-6.8.1/include/linux/mfd/samsung/s2mpu02.h
Normal file
|
|
@ -0,0 +1,189 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd
|
||||
* http://www.samsung.com
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_S2MPU02_H
|
||||
#define __LINUX_MFD_S2MPU02_H
|
||||
|
||||
/* S2MPU02 registers */
|
||||
enum S2MPU02_reg {
|
||||
S2MPU02_REG_ID,
|
||||
S2MPU02_REG_INT1,
|
||||
S2MPU02_REG_INT2,
|
||||
S2MPU02_REG_INT3,
|
||||
S2MPU02_REG_INT1M,
|
||||
S2MPU02_REG_INT2M,
|
||||
S2MPU02_REG_INT3M,
|
||||
S2MPU02_REG_ST1,
|
||||
S2MPU02_REG_ST2,
|
||||
S2MPU02_REG_PWRONSRC,
|
||||
S2MPU02_REG_OFFSRC,
|
||||
S2MPU02_REG_BU_CHG,
|
||||
S2MPU02_REG_RTCCTRL,
|
||||
S2MPU02_REG_PMCTRL1,
|
||||
S2MPU02_REG_RSVD1,
|
||||
S2MPU02_REG_RSVD2,
|
||||
S2MPU02_REG_RSVD3,
|
||||
S2MPU02_REG_RSVD4,
|
||||
S2MPU02_REG_RSVD5,
|
||||
S2MPU02_REG_RSVD6,
|
||||
S2MPU02_REG_RSVD7,
|
||||
S2MPU02_REG_WRSTEN,
|
||||
S2MPU02_REG_RSVD8,
|
||||
S2MPU02_REG_RSVD9,
|
||||
S2MPU02_REG_RSVD10,
|
||||
S2MPU02_REG_B1CTRL1,
|
||||
S2MPU02_REG_B1CTRL2,
|
||||
S2MPU02_REG_B2CTRL1,
|
||||
S2MPU02_REG_B2CTRL2,
|
||||
S2MPU02_REG_B3CTRL1,
|
||||
S2MPU02_REG_B3CTRL2,
|
||||
S2MPU02_REG_B4CTRL1,
|
||||
S2MPU02_REG_B4CTRL2,
|
||||
S2MPU02_REG_B5CTRL1,
|
||||
S2MPU02_REG_B5CTRL2,
|
||||
S2MPU02_REG_B5CTRL3,
|
||||
S2MPU02_REG_B5CTRL4,
|
||||
S2MPU02_REG_B5CTRL5,
|
||||
S2MPU02_REG_B6CTRL1,
|
||||
S2MPU02_REG_B6CTRL2,
|
||||
S2MPU02_REG_B7CTRL1,
|
||||
S2MPU02_REG_B7CTRL2,
|
||||
S2MPU02_REG_RAMP1,
|
||||
S2MPU02_REG_RAMP2,
|
||||
S2MPU02_REG_L1CTRL,
|
||||
S2MPU02_REG_L2CTRL1,
|
||||
S2MPU02_REG_L2CTRL2,
|
||||
S2MPU02_REG_L2CTRL3,
|
||||
S2MPU02_REG_L2CTRL4,
|
||||
S2MPU02_REG_L3CTRL,
|
||||
S2MPU02_REG_L4CTRL,
|
||||
S2MPU02_REG_L5CTRL,
|
||||
S2MPU02_REG_L6CTRL,
|
||||
S2MPU02_REG_L7CTRL,
|
||||
S2MPU02_REG_L8CTRL,
|
||||
S2MPU02_REG_L9CTRL,
|
||||
S2MPU02_REG_L10CTRL,
|
||||
S2MPU02_REG_L11CTRL,
|
||||
S2MPU02_REG_L12CTRL,
|
||||
S2MPU02_REG_L13CTRL,
|
||||
S2MPU02_REG_L14CTRL,
|
||||
S2MPU02_REG_L15CTRL,
|
||||
S2MPU02_REG_L16CTRL,
|
||||
S2MPU02_REG_L17CTRL,
|
||||
S2MPU02_REG_L18CTRL,
|
||||
S2MPU02_REG_L19CTRL,
|
||||
S2MPU02_REG_L20CTRL,
|
||||
S2MPU02_REG_L21CTRL,
|
||||
S2MPU02_REG_L22CTRL,
|
||||
S2MPU02_REG_L23CTRL,
|
||||
S2MPU02_REG_L24CTRL,
|
||||
S2MPU02_REG_L25CTRL,
|
||||
S2MPU02_REG_L26CTRL,
|
||||
S2MPU02_REG_L27CTRL,
|
||||
S2MPU02_REG_L28CTRL,
|
||||
S2MPU02_REG_LDODSCH1,
|
||||
S2MPU02_REG_LDODSCH2,
|
||||
S2MPU02_REG_LDODSCH3,
|
||||
S2MPU02_REG_LDODSCH4,
|
||||
S2MPU02_REG_SELMIF,
|
||||
S2MPU02_REG_RSVD11,
|
||||
S2MPU02_REG_RSVD12,
|
||||
S2MPU02_REG_RSVD13,
|
||||
S2MPU02_REG_DVSSEL,
|
||||
S2MPU02_REG_DVSPTR,
|
||||
S2MPU02_REG_DVSDATA,
|
||||
};
|
||||
|
||||
/* S2MPU02 regulator ids */
|
||||
enum S2MPU02_regulators {
|
||||
S2MPU02_LDO1,
|
||||
S2MPU02_LDO2,
|
||||
S2MPU02_LDO3,
|
||||
S2MPU02_LDO4,
|
||||
S2MPU02_LDO5,
|
||||
S2MPU02_LDO6,
|
||||
S2MPU02_LDO7,
|
||||
S2MPU02_LDO8,
|
||||
S2MPU02_LDO9,
|
||||
S2MPU02_LDO10,
|
||||
S2MPU02_LDO11,
|
||||
S2MPU02_LDO12,
|
||||
S2MPU02_LDO13,
|
||||
S2MPU02_LDO14,
|
||||
S2MPU02_LDO15,
|
||||
S2MPU02_LDO16,
|
||||
S2MPU02_LDO17,
|
||||
S2MPU02_LDO18,
|
||||
S2MPU02_LDO19,
|
||||
S2MPU02_LDO20,
|
||||
S2MPU02_LDO21,
|
||||
S2MPU02_LDO22,
|
||||
S2MPU02_LDO23,
|
||||
S2MPU02_LDO24,
|
||||
S2MPU02_LDO25,
|
||||
S2MPU02_LDO26,
|
||||
S2MPU02_LDO27,
|
||||
S2MPU02_LDO28,
|
||||
S2MPU02_BUCK1,
|
||||
S2MPU02_BUCK2,
|
||||
S2MPU02_BUCK3,
|
||||
S2MPU02_BUCK4,
|
||||
S2MPU02_BUCK5,
|
||||
S2MPU02_BUCK6,
|
||||
S2MPU02_BUCK7,
|
||||
|
||||
S2MPU02_REGULATOR_MAX,
|
||||
};
|
||||
|
||||
/* Regulator constraints for BUCKx */
|
||||
#define S2MPU02_BUCK1234_MIN_600MV 600000
|
||||
#define S2MPU02_BUCK5_MIN_1081_25MV 1081250
|
||||
#define S2MPU02_BUCK6_MIN_1700MV 1700000
|
||||
#define S2MPU02_BUCK7_MIN_900MV 900000
|
||||
|
||||
#define S2MPU02_BUCK1234_STEP_6_25MV 6250
|
||||
#define S2MPU02_BUCK5_STEP_6_25MV 6250
|
||||
#define S2MPU02_BUCK6_STEP_2_50MV 2500
|
||||
#define S2MPU02_BUCK7_STEP_6_25MV 6250
|
||||
|
||||
#define S2MPU02_BUCK1234_START_SEL 0x00
|
||||
#define S2MPU02_BUCK5_START_SEL 0x4D
|
||||
#define S2MPU02_BUCK6_START_SEL 0x28
|
||||
#define S2MPU02_BUCK7_START_SEL 0x30
|
||||
|
||||
#define S2MPU02_BUCK_RAMP_DELAY 12500
|
||||
|
||||
/* Regulator constraints for different types of LDOx */
|
||||
#define S2MPU02_LDO_MIN_900MV 900000
|
||||
#define S2MPU02_LDO_MIN_1050MV 1050000
|
||||
#define S2MPU02_LDO_MIN_1600MV 1600000
|
||||
#define S2MPU02_LDO_STEP_12_5MV 12500
|
||||
#define S2MPU02_LDO_STEP_25MV 25000
|
||||
#define S2MPU02_LDO_STEP_50MV 50000
|
||||
|
||||
#define S2MPU02_LDO_GROUP1_START_SEL 0x8
|
||||
#define S2MPU02_LDO_GROUP2_START_SEL 0xA
|
||||
#define S2MPU02_LDO_GROUP3_START_SEL 0x10
|
||||
|
||||
#define S2MPU02_LDO_VSEL_MASK 0x3F
|
||||
#define S2MPU02_BUCK_VSEL_MASK 0xFF
|
||||
#define S2MPU02_ENABLE_MASK (0x03 << S2MPU02_ENABLE_SHIFT)
|
||||
#define S2MPU02_ENABLE_SHIFT 6
|
||||
|
||||
/* On/Off controlled by PWREN */
|
||||
#define S2MPU02_ENABLE_SUSPEND (0x01 << S2MPU02_ENABLE_SHIFT)
|
||||
#define S2MPU02_DISABLE_SUSPEND (0x11 << S2MPU02_ENABLE_SHIFT)
|
||||
#define S2MPU02_LDO_N_VOLTAGES (S2MPU02_LDO_VSEL_MASK + 1)
|
||||
#define S2MPU02_BUCK_N_VOLTAGES (S2MPU02_BUCK_VSEL_MASK + 1)
|
||||
|
||||
/* RAMP delay for BUCK1234*/
|
||||
#define S2MPU02_BUCK1_RAMP_SHIFT 6
|
||||
#define S2MPU02_BUCK2_RAMP_SHIFT 4
|
||||
#define S2MPU02_BUCK3_RAMP_SHIFT 2
|
||||
#define S2MPU02_BUCK4_RAMP_SHIFT 0
|
||||
#define S2MPU02_BUCK1234_RAMP_MASK 0x3
|
||||
|
||||
#endif /* __LINUX_MFD_S2MPU02_H */
|
||||
205
linux-6.8.1/include/linux/mfd/samsung/s5m8767.h
Normal file
205
linux-6.8.1/include/linux/mfd/samsung/s5m8767.h
Normal file
|
|
@ -0,0 +1,205 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd
|
||||
* http://www.samsung.com
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_S5M8767_H
|
||||
#define __LINUX_MFD_S5M8767_H
|
||||
|
||||
/* S5M8767 registers */
|
||||
enum s5m8767_reg {
|
||||
S5M8767_REG_ID,
|
||||
S5M8767_REG_INT1,
|
||||
S5M8767_REG_INT2,
|
||||
S5M8767_REG_INT3,
|
||||
S5M8767_REG_INT1M,
|
||||
S5M8767_REG_INT2M,
|
||||
S5M8767_REG_INT3M,
|
||||
S5M8767_REG_STATUS1,
|
||||
S5M8767_REG_STATUS2,
|
||||
S5M8767_REG_STATUS3,
|
||||
S5M8767_REG_CTRL1,
|
||||
S5M8767_REG_CTRL2,
|
||||
S5M8767_REG_LOWBAT1,
|
||||
S5M8767_REG_LOWBAT2,
|
||||
S5M8767_REG_BUCHG,
|
||||
S5M8767_REG_DVSRAMP,
|
||||
S5M8767_REG_DVSTIMER2 = 0x10,
|
||||
S5M8767_REG_DVSTIMER3,
|
||||
S5M8767_REG_DVSTIMER4,
|
||||
S5M8767_REG_LDO1,
|
||||
S5M8767_REG_LDO2,
|
||||
S5M8767_REG_LDO3,
|
||||
S5M8767_REG_LDO4,
|
||||
S5M8767_REG_LDO5,
|
||||
S5M8767_REG_LDO6,
|
||||
S5M8767_REG_LDO7,
|
||||
S5M8767_REG_LDO8,
|
||||
S5M8767_REG_LDO9,
|
||||
S5M8767_REG_LDO10,
|
||||
S5M8767_REG_LDO11,
|
||||
S5M8767_REG_LDO12,
|
||||
S5M8767_REG_LDO13,
|
||||
S5M8767_REG_LDO14 = 0x20,
|
||||
S5M8767_REG_LDO15,
|
||||
S5M8767_REG_LDO16,
|
||||
S5M8767_REG_LDO17,
|
||||
S5M8767_REG_LDO18,
|
||||
S5M8767_REG_LDO19,
|
||||
S5M8767_REG_LDO20,
|
||||
S5M8767_REG_LDO21,
|
||||
S5M8767_REG_LDO22,
|
||||
S5M8767_REG_LDO23,
|
||||
S5M8767_REG_LDO24,
|
||||
S5M8767_REG_LDO25,
|
||||
S5M8767_REG_LDO26,
|
||||
S5M8767_REG_LDO27,
|
||||
S5M8767_REG_LDO28,
|
||||
S5M8767_REG_UVLO = 0x31,
|
||||
S5M8767_REG_BUCK1CTRL1,
|
||||
S5M8767_REG_BUCK1CTRL2,
|
||||
S5M8767_REG_BUCK2CTRL,
|
||||
S5M8767_REG_BUCK2DVS1,
|
||||
S5M8767_REG_BUCK2DVS2,
|
||||
S5M8767_REG_BUCK2DVS3,
|
||||
S5M8767_REG_BUCK2DVS4,
|
||||
S5M8767_REG_BUCK2DVS5,
|
||||
S5M8767_REG_BUCK2DVS6,
|
||||
S5M8767_REG_BUCK2DVS7,
|
||||
S5M8767_REG_BUCK2DVS8,
|
||||
S5M8767_REG_BUCK3CTRL,
|
||||
S5M8767_REG_BUCK3DVS1,
|
||||
S5M8767_REG_BUCK3DVS2,
|
||||
S5M8767_REG_BUCK3DVS3,
|
||||
S5M8767_REG_BUCK3DVS4,
|
||||
S5M8767_REG_BUCK3DVS5,
|
||||
S5M8767_REG_BUCK3DVS6,
|
||||
S5M8767_REG_BUCK3DVS7,
|
||||
S5M8767_REG_BUCK3DVS8,
|
||||
S5M8767_REG_BUCK4CTRL,
|
||||
S5M8767_REG_BUCK4DVS1,
|
||||
S5M8767_REG_BUCK4DVS2,
|
||||
S5M8767_REG_BUCK4DVS3,
|
||||
S5M8767_REG_BUCK4DVS4,
|
||||
S5M8767_REG_BUCK4DVS5,
|
||||
S5M8767_REG_BUCK4DVS6,
|
||||
S5M8767_REG_BUCK4DVS7,
|
||||
S5M8767_REG_BUCK4DVS8,
|
||||
S5M8767_REG_BUCK5CTRL1,
|
||||
S5M8767_REG_BUCK5CTRL2,
|
||||
S5M8767_REG_BUCK5CTRL3,
|
||||
S5M8767_REG_BUCK5CTRL4,
|
||||
S5M8767_REG_BUCK5CTRL5,
|
||||
S5M8767_REG_BUCK6CTRL1,
|
||||
S5M8767_REG_BUCK6CTRL2,
|
||||
S5M8767_REG_BUCK7CTRL1,
|
||||
S5M8767_REG_BUCK7CTRL2,
|
||||
S5M8767_REG_BUCK8CTRL1,
|
||||
S5M8767_REG_BUCK8CTRL2,
|
||||
S5M8767_REG_BUCK9CTRL1,
|
||||
S5M8767_REG_BUCK9CTRL2,
|
||||
S5M8767_REG_LDO1CTRL,
|
||||
S5M8767_REG_LDO2_1CTRL,
|
||||
S5M8767_REG_LDO2_2CTRL,
|
||||
S5M8767_REG_LDO2_3CTRL,
|
||||
S5M8767_REG_LDO2_4CTRL,
|
||||
S5M8767_REG_LDO3CTRL,
|
||||
S5M8767_REG_LDO4CTRL,
|
||||
S5M8767_REG_LDO5CTRL,
|
||||
S5M8767_REG_LDO6CTRL,
|
||||
S5M8767_REG_LDO7CTRL,
|
||||
S5M8767_REG_LDO8CTRL,
|
||||
S5M8767_REG_LDO9CTRL,
|
||||
S5M8767_REG_LDO10CTRL,
|
||||
S5M8767_REG_LDO11CTRL,
|
||||
S5M8767_REG_LDO12CTRL,
|
||||
S5M8767_REG_LDO13CTRL,
|
||||
S5M8767_REG_LDO14CTRL,
|
||||
S5M8767_REG_LDO15CTRL,
|
||||
S5M8767_REG_LDO16CTRL,
|
||||
S5M8767_REG_LDO17CTRL,
|
||||
S5M8767_REG_LDO18CTRL,
|
||||
S5M8767_REG_LDO19CTRL,
|
||||
S5M8767_REG_LDO20CTRL,
|
||||
S5M8767_REG_LDO21CTRL,
|
||||
S5M8767_REG_LDO22CTRL,
|
||||
S5M8767_REG_LDO23CTRL,
|
||||
S5M8767_REG_LDO24CTRL,
|
||||
S5M8767_REG_LDO25CTRL,
|
||||
S5M8767_REG_LDO26CTRL,
|
||||
S5M8767_REG_LDO27CTRL,
|
||||
S5M8767_REG_LDO28CTRL,
|
||||
};
|
||||
|
||||
/* S5M8767 regulator ids */
|
||||
enum s5m8767_regulators {
|
||||
S5M8767_LDO1,
|
||||
S5M8767_LDO2,
|
||||
S5M8767_LDO3,
|
||||
S5M8767_LDO4,
|
||||
S5M8767_LDO5,
|
||||
S5M8767_LDO6,
|
||||
S5M8767_LDO7,
|
||||
S5M8767_LDO8,
|
||||
S5M8767_LDO9,
|
||||
S5M8767_LDO10,
|
||||
S5M8767_LDO11,
|
||||
S5M8767_LDO12,
|
||||
S5M8767_LDO13,
|
||||
S5M8767_LDO14,
|
||||
S5M8767_LDO15,
|
||||
S5M8767_LDO16,
|
||||
S5M8767_LDO17,
|
||||
S5M8767_LDO18,
|
||||
S5M8767_LDO19,
|
||||
S5M8767_LDO20,
|
||||
S5M8767_LDO21,
|
||||
S5M8767_LDO22,
|
||||
S5M8767_LDO23,
|
||||
S5M8767_LDO24,
|
||||
S5M8767_LDO25,
|
||||
S5M8767_LDO26,
|
||||
S5M8767_LDO27,
|
||||
S5M8767_LDO28,
|
||||
S5M8767_BUCK1,
|
||||
S5M8767_BUCK2,
|
||||
S5M8767_BUCK3,
|
||||
S5M8767_BUCK4,
|
||||
S5M8767_BUCK5,
|
||||
S5M8767_BUCK6,
|
||||
S5M8767_BUCK7,
|
||||
S5M8767_BUCK8,
|
||||
S5M8767_BUCK9,
|
||||
S5M8767_AP_EN32KHZ,
|
||||
S5M8767_CP_EN32KHZ,
|
||||
|
||||
S5M8767_REG_MAX,
|
||||
};
|
||||
|
||||
/* LDO_EN/BUCK_EN field in registers */
|
||||
#define S5M8767_ENCTRL_SHIFT 6
|
||||
#define S5M8767_ENCTRL_MASK (0x3 << S5M8767_ENCTRL_SHIFT)
|
||||
|
||||
/*
|
||||
* LDO_EN/BUCK_EN register value for controlling this Buck or LDO
|
||||
* by GPIO (PWREN, BUCKEN).
|
||||
*/
|
||||
#define S5M8767_ENCTRL_USE_GPIO 0x1
|
||||
|
||||
/*
|
||||
* Values for BUCK_RAMP field in DVS_RAMP register, matching raw values
|
||||
* in mV/us.
|
||||
*/
|
||||
enum s5m8767_dvs_buck_ramp_values {
|
||||
S5M8767_DVS_BUCK_RAMP_5 = 0x4,
|
||||
S5M8767_DVS_BUCK_RAMP_10 = 0x9,
|
||||
S5M8767_DVS_BUCK_RAMP_12_5 = 0xb,
|
||||
S5M8767_DVS_BUCK_RAMP_25 = 0xd,
|
||||
S5M8767_DVS_BUCK_RAMP_50 = 0xe,
|
||||
S5M8767_DVS_BUCK_RAMP_100 = 0xf,
|
||||
};
|
||||
#define S5M8767_DVS_BUCK_RAMP_SHIFT 4
|
||||
#define S5M8767_DVS_BUCK_RAMP_MASK (0xf << S5M8767_DVS_BUCK_RAMP_SHIFT)
|
||||
|
||||
#endif /* __LINUX_MFD_S5M8767_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue