282 lines
9.5 KiB
YAML
282 lines
9.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8 Audio Clock Mux
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maintainers:
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- Shengjiu Wang <shengjiu.wang@nxp.com>
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description: |
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NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP
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used to control Audio related clock on the SoC.
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properties:
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compatible:
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enum:
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- fsl,imx8dxl-acm
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- fsl,imx8qm-acm
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- fsl,imx8qxp-acm
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reg:
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maxItems: 1
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power-domains:
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minItems: 13
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maxItems: 21
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'#clock-cells':
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const: 1
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description:
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h
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for the full list of i.MX8 ACM clock IDs.
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clocks:
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minItems: 13
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maxItems: 27
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clock-names:
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minItems: 13
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maxItems: 27
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required:
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- compatible
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- reg
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- power-domains
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- '#clock-cells'
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- clocks
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- clock-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qxp-acm
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then:
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properties:
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power-domains:
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items:
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- description: power domain of IMX_SC_R_AUDIO_CLK_0
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- description: power domain of IMX_SC_R_AUDIO_CLK_1
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- description: power domain of IMX_SC_R_MCLK_OUT_0
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- description: power domain of IMX_SC_R_MCLK_OUT_1
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- description: power domain of IMX_SC_R_AUDIO_PLL_0
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- description: power domain of IMX_SC_R_AUDIO_PLL_1
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- description: power domain of IMX_SC_R_ASRC_0
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- description: power domain of IMX_SC_R_ASRC_1
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- description: power domain of IMX_SC_R_ESAI_0
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- description: power domain of IMX_SC_R_SAI_0
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- description: power domain of IMX_SC_R_SAI_1
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- description: power domain of IMX_SC_R_SAI_2
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- description: power domain of IMX_SC_R_SAI_3
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- description: power domain of IMX_SC_R_SAI_4
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- description: power domain of IMX_SC_R_SAI_5
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- description: power domain of IMX_SC_R_SPDIF_0
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- description: power domain of IMX_SC_R_MQS_0
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clocks:
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minItems: 18
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maxItems: 18
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clock-names:
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items:
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- const: aud_rec_clk0_lpcg_clk
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- const: aud_rec_clk1_lpcg_clk
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- const: aud_pll_div_clk0_lpcg_clk
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- const: aud_pll_div_clk1_lpcg_clk
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- const: ext_aud_mclk0
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- const: ext_aud_mclk1
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- const: esai0_rx_clk
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- const: esai0_rx_hf_clk
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- const: esai0_tx_clk
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- const: esai0_tx_hf_clk
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- const: spdif0_rx
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- const: sai0_rx_bclk
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- const: sai0_tx_bclk
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- const: sai1_rx_bclk
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- const: sai1_tx_bclk
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- const: sai2_rx_bclk
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- const: sai3_rx_bclk
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- const: sai4_rx_bclk
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qm-acm
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then:
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properties:
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power-domains:
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items:
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- description: power domain of IMX_SC_R_AUDIO_CLK_0
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- description: power domain of IMX_SC_R_AUDIO_CLK_1
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- description: power domain of IMX_SC_R_MCLK_OUT_0
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- description: power domain of IMX_SC_R_MCLK_OUT_1
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- description: power domain of IMX_SC_R_AUDIO_PLL_0
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- description: power domain of IMX_SC_R_AUDIO_PLL_1
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- description: power domain of IMX_SC_R_ASRC_0
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- description: power domain of IMX_SC_R_ASRC_1
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- description: power domain of IMX_SC_R_ESAI_0
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- description: power domain of IMX_SC_R_ESAI_1
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- description: power domain of IMX_SC_R_SAI_0
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- description: power domain of IMX_SC_R_SAI_1
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- description: power domain of IMX_SC_R_SAI_2
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- description: power domain of IMX_SC_R_SAI_3
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- description: power domain of IMX_SC_R_SAI_4
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- description: power domain of IMX_SC_R_SAI_5
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- description: power domain of IMX_SC_R_SAI_6
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- description: power domain of IMX_SC_R_SAI_7
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- description: power domain of IMX_SC_R_SPDIF_0
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- description: power domain of IMX_SC_R_SPDIF_1
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- description: power domain of IMX_SC_R_MQS_0
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clocks:
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minItems: 27
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maxItems: 27
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clock-names:
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items:
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- const: aud_rec_clk0_lpcg_clk
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- const: aud_rec_clk1_lpcg_clk
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- const: aud_pll_div_clk0_lpcg_clk
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- const: aud_pll_div_clk1_lpcg_clk
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- const: mlb_clk
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- const: hdmi_rx_mclk
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- const: ext_aud_mclk0
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- const: ext_aud_mclk1
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- const: esai0_rx_clk
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- const: esai0_rx_hf_clk
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- const: esai0_tx_clk
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- const: esai0_tx_hf_clk
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- const: esai1_rx_clk
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- const: esai1_rx_hf_clk
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- const: esai1_tx_clk
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- const: esai1_tx_hf_clk
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- const: spdif0_rx
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- const: spdif1_rx
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- const: sai0_rx_bclk
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- const: sai0_tx_bclk
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- const: sai1_rx_bclk
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- const: sai1_tx_bclk
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- const: sai2_rx_bclk
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- const: sai3_rx_bclk
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- const: sai4_rx_bclk
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- const: sai5_tx_bclk
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- const: sai6_rx_bclk
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8dxl-acm
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then:
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properties:
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power-domains:
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items:
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- description: power domain of IMX_SC_R_AUDIO_CLK_0
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- description: power domain of IMX_SC_R_AUDIO_CLK_1
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- description: power domain of IMX_SC_R_MCLK_OUT_0
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- description: power domain of IMX_SC_R_MCLK_OUT_1
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- description: power domain of IMX_SC_R_AUDIO_PLL_0
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- description: power domain of IMX_SC_R_AUDIO_PLL_1
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- description: power domain of IMX_SC_R_ASRC_0
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- description: power domain of IMX_SC_R_SAI_0
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- description: power domain of IMX_SC_R_SAI_1
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- description: power domain of IMX_SC_R_SAI_2
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- description: power domain of IMX_SC_R_SAI_3
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- description: power domain of IMX_SC_R_SPDIF_0
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- description: power domain of IMX_SC_R_MQS_0
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clocks:
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minItems: 13
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maxItems: 13
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clock-names:
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items:
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- const: aud_rec_clk0_lpcg_clk
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- const: aud_rec_clk1_lpcg_clk
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- const: aud_pll_div_clk0_lpcg_clk
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- const: aud_pll_div_clk1_lpcg_clk
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- const: ext_aud_mclk0
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- const: ext_aud_mclk1
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- const: spdif0_rx
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- const: sai0_rx_bclk
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- const: sai0_tx_bclk
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- const: sai1_rx_bclk
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- const: sai1_tx_bclk
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- const: sai2_rx_bclk
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- const: sai3_rx_bclk
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additionalProperties: false
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examples:
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# Clock Control Module node:
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- |
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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clock-controller@59e00000 {
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compatible = "fsl,imx8qxp-acm";
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reg = <0x59e00000 0x1d0000>;
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#clock-cells = <1>;
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power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
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<&pd IMX_SC_R_AUDIO_CLK_1>,
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<&pd IMX_SC_R_MCLK_OUT_0>,
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<&pd IMX_SC_R_MCLK_OUT_1>,
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<&pd IMX_SC_R_AUDIO_PLL_0>,
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<&pd IMX_SC_R_AUDIO_PLL_1>,
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<&pd IMX_SC_R_ASRC_0>,
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<&pd IMX_SC_R_ASRC_1>,
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<&pd IMX_SC_R_ESAI_0>,
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<&pd IMX_SC_R_SAI_0>,
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<&pd IMX_SC_R_SAI_1>,
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<&pd IMX_SC_R_SAI_2>,
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<&pd IMX_SC_R_SAI_3>,
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<&pd IMX_SC_R_SAI_4>,
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<&pd IMX_SC_R_SAI_5>,
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<&pd IMX_SC_R_SPDIF_0>,
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<&pd IMX_SC_R_MQS_0>;
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clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,
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<&aud_rec1_lpcg IMX_LPCG_CLK_0>,
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<&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
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<&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
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<&clk_ext_aud_mclk0>,
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<&clk_ext_aud_mclk1>,
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<&clk_esai0_rx_clk>,
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<&clk_esai0_rx_hf_clk>,
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<&clk_esai0_tx_clk>,
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<&clk_esai0_tx_hf_clk>,
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<&clk_spdif0_rx>,
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<&clk_sai0_rx_bclk>,
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<&clk_sai0_tx_bclk>,
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<&clk_sai1_rx_bclk>,
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<&clk_sai1_tx_bclk>,
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<&clk_sai2_rx_bclk>,
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<&clk_sai3_rx_bclk>,
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<&clk_sai4_rx_bclk>;
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clock-names = "aud_rec_clk0_lpcg_clk",
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"aud_rec_clk1_lpcg_clk",
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"aud_pll_div_clk0_lpcg_clk",
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"aud_pll_div_clk1_lpcg_clk",
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"ext_aud_mclk0",
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"ext_aud_mclk1",
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"esai0_rx_clk",
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"esai0_rx_hf_clk",
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"esai0_tx_clk",
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"esai0_tx_hf_clk",
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"spdif0_rx",
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"sai0_rx_bclk",
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"sai0_tx_bclk",
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"sai1_rx_bclk",
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"sai1_tx_bclk",
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"sai2_rx_bclk",
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"sai3_rx_bclk",
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"sai4_rx_bclk";
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};
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