265 lines
7 KiB
YAML
265 lines
7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/silabs,si5351.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Silicon Labs Si5351A/B/C programmable I2C clock generators
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description: |
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The Silicon Labs Si5351A/B/C are programmable I2C clock generators with up to
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8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
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output clocks are accessible. The internal structure of the clock generators
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can be found in [1].
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[1] Si5351A/B/C Data Sheet
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https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
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maintainers:
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- Alvin Šipraga <alsi@bang-olufsen.dk>
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properties:
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compatible:
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enum:
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- silabs,si5351a # Si5351A, 20-QFN package
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- silabs,si5351a-msop # Si5351A, 10-MSOP package
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- silabs,si5351b # Si5351B, 20-QFN package
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- silabs,si5351c # Si5351C, 20-QFN package
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reg:
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enum:
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- 0x60
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- 0x61
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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"#clock-cells":
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const: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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items:
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- const: xtal
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- const: clkin
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silabs,pll-source:
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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description: |
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A list of cell pairs containing a PLL index and its source. Allows to
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overwrite clock source of the internal PLLs.
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items:
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items:
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- description: PLL A (0) or PLL B (1)
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enum: [ 0, 1 ]
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- description: PLL source, XTAL (0) or CLKIN (1, Si5351C only).
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enum: [ 0, 1 ]
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silabs,pll-reset-mode:
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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minItems: 1
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maxItems: 2
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description: A list of cell pairs containing a PLL index and its reset mode.
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items:
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items:
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- description: PLL A (0) or PLL B (1)
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enum: [ 0, 1 ]
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- description: |
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Reset mode for the PLL. Mode can be one of:
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0 - reset whenever PLL rate is adjusted (default mode)
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1 - do not reset when PLL rate is adjusted
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In mode 1, the PLL is only reset if the silabs,pll-reset is
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specified in one of the clock output child nodes that also sources
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the PLL. This mode may be preferable if output clocks are expected
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to be adjusted without glitches.
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enum: [ 0, 1 ]
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patternProperties:
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"^clkout@[0-7]$":
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type: object
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additionalProperties: false
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properties:
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reg:
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description: Clock output number.
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clock-frequency: true
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silabs,clock-source:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Source clock of the this output's divider stage.
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0 - use multisynth N for this output, where N is the output number
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1 - use either multisynth 0 (if output number is 0-3) or multisynth 4
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(otherwise) for this output
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2 - use XTAL for this output
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3 - use CLKIN for this output (Si5351C only)
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silabs,drive-strength:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 2, 4, 6, 8 ]
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description: Output drive strength in mA.
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silabs,multisynth-source:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1 ]
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description:
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Source PLL A (0) or B (1) for the corresponding multisynth divider.
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silabs,pll-master:
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type: boolean
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description: |
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The frequency of the source PLL is allowed to be changed by the
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multisynth when setting the rate of this clock output.
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silabs,pll-reset:
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type: boolean
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description: Reset the source PLL when enabling this clock output.
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silabs,disable-state:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1, 2, 3 ]
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description: |
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Clock output disable state. The state can be one of:
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0 - clock output is driven LOW when disabled
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1 - clock output is driven HIGH when disabled
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2 - clock output is FLOATING (HIGH-Z) when disabled
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3 - clock output is never disabled
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: silabs,si5351a-msop
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then:
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properties:
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reg:
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maximum: 2
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else:
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properties:
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reg:
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maximum: 7
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- if:
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properties:
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compatible:
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contains:
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const: silabs,si5351c
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then:
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properties:
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silabs,clock-source:
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enum: [ 0, 1, 2, 3 ]
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else:
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properties:
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silabs,clock-source:
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enum: [ 0, 1, 2 ]
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required:
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- reg
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- silabs,si5351a
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- silabs,si5351a-msop
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- silabs,si5351b
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then:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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maxItems: 1
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required:
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- reg
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- "#address-cells"
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- "#size-cells"
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- "#clock-cells"
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-generator@60 {
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compatible = "silabs,si5351a-msop";
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reg = <0x60>;
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <1>;
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/* Connect XTAL input to 25MHz reference */
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clocks = <&ref25>;
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clock-names = "xtal";
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/* Use XTAL input as source of PLL0 and PLL1 */
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silabs,pll-source = <0 0>, <1 0>;
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/* Don't reset PLL1 on rate adjustment */
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silabs,pll-reset-mode = <1 1>;
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/*
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* Overwrite CLK0 configuration with:
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* - 8 mA output drive strength
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* - PLL0 as clock source of multisynth 0
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* - Multisynth 0 as clock source of output divider
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* - Multisynth 0 can change PLL0
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* - Set initial clock frequency of 74.25MHz
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*/
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clkout@0 {
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reg = <0>;
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silabs,drive-strength = <8>;
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silabs,multisynth-source = <0>;
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silabs,clock-source = <0>;
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silabs,pll-master;
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clock-frequency = <74250000>;
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};
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/*
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* Overwrite CLK1 configuration with:
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* - 4 mA output drive strength
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* - PLL1 as clock source of multisynth 1
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* - Multisynth 1 as clock source of output divider
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* - Multisynth 1 can change PLL1
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* - Reset PLL1 when enabling this clock output
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*/
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clkout@1 {
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reg = <1>;
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silabs,drive-strength = <4>;
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silabs,multisynth-source = <1>;
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silabs,clock-source = <0>;
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silabs,pll-master;
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silabs,pll-reset;
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};
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/*
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* Overwrite CLK2 configuration with:
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* - XTAL as clock source of output divider
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*/
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clkout@2 {
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reg = <2>;
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silabs,clock-source = <2>;
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};
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};
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};
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