130 lines
2.9 KiB
YAML
130 lines
2.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/renesas,shmobile-lcdc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas SH-Mobile LCD Controller (LCDC)
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maintainers:
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- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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- Geert Uytterhoeven <geert+renesas@glider.be>
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properties:
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compatible:
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enum:
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- renesas,r8a7740-lcdc # R-Mobile A1
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- renesas,sh73a0-lcdc # SH-Mobile AG5
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 5
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description:
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Only the functional clock is mandatory.
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Some of the optional clocks are model-dependent (e.g. "video" (a.k.a.
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"vou" or "dv_clk") is available on R-Mobile A1 only).
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clock-names:
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minItems: 1
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items:
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- const: fck
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- enum: [ media, lclk, hdmi, video ]
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- enum: [ media, lclk, hdmi, video ]
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- enum: [ media, lclk, hdmi, video ]
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- enum: [ media, lclk, hdmi, video ]
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power-domains:
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: LCD port (R-Mobile A1 and SH-Mobile AG5)
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unevaluatedProperties: false
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: HDMI port (R-Mobile A1 LCDC1 and SH-Mobile AG5)
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unevaluatedProperties: false
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port@2:
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$ref: /schemas/graph.yaml#/properties/port
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description: MIPI-DSI port (SH-Mobile AG5)
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unevaluatedProperties: false
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required:
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- port@0
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- power-domains
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- ports
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r8a7740-lcdc
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then:
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properties:
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ports:
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properties:
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port@2: false
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- if:
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properties:
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compatible:
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contains:
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const: renesas,sh73a0-lcdc
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then:
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properties:
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ports:
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required:
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- port@1
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- port@2
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examples:
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- |
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#include <dt-bindings/clock/r8a7740-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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lcd-controller@fe940000 {
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compatible = "renesas,r8a7740-lcdc";
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reg = <0xfe940000 0x4000>;
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7740_CLK_LCDC0>,
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<&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk0_clk>,
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<&vou_clk>;
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clock-names = "fck", "media", "lclk", "video";
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power-domains = <&pd_a4lc>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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lcdc0_rgb: endpoint {
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};
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};
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};
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};
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