97 lines
1.9 KiB
YAML
97 lines
1.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-pcie-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm QMP PHY controller (PCIe, MSM8998)
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maintainers:
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- Vinod Koul <vkoul@kernel.org>
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description:
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The QMP PHY controller supports physical layer functionality for a number of
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controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
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properties:
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compatible:
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const: qcom,msm8998-qmp-pcie-phy
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reg:
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items:
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- description: serdes
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: aux
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- const: cfg_ahb
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- const: ref
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- const: pipe
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: phy
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- const: common
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vdda-phy-supply: true
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vdda-pll-supply: true
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"#clock-cells":
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const: 0
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clock-output-names:
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maxItems: 1
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"#phy-cells":
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- vdda-phy-supply
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- vdda-pll-supply
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- "#clock-cells"
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- clock-output-names
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-msm8998.h>
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phy@1c18000 {
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compatible = "qcom,msm8998-qmp-pcie-phy";
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reg = <0x01c06000 0x1000>;
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clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_CLKREF_CLK>,
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<&gcc GCC_PCIE_0_PIPE_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"ref",
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"pipe";
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clock-output-names = "pcie_0_pipe_clk_src";
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#clock-cells = <0>;
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#phy-cells = <0>;
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resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
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reset-names = "phy", "common";
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vdda-phy-supply = <&vreg_l1a_0p875>;
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vdda-pll-supply = <&vreg_l2a_1p2>;
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};
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