183 lines
4.2 KiB
C
183 lines
4.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */
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#include <linux/ethtool.h>
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#include <linux/iopoll.h>
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#include <linux/pci.h>
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#include <linux/phy.h>
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#include "../libwx/wx_type.h"
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#include "../libwx/wx_hw.h"
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#include "ngbe_type.h"
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#include "ngbe_mdio.h"
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static int ngbe_phy_read_reg_internal(struct mii_bus *bus, int phy_addr, int regnum)
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{
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struct wx *wx = bus->priv;
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if (phy_addr != 0)
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return 0xffff;
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return (u16)rd32(wx, NGBE_PHY_CONFIG(regnum));
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}
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static int ngbe_phy_write_reg_internal(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
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{
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struct wx *wx = bus->priv;
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if (phy_addr == 0)
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wr32(wx, NGBE_PHY_CONFIG(regnum), value);
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return 0;
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}
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static int ngbe_phy_read_reg_c22(struct mii_bus *bus, int phy_addr, int regnum)
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{
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struct wx *wx = bus->priv;
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u16 phy_data;
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if (wx->mac_type == em_mac_type_mdi)
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phy_data = ngbe_phy_read_reg_internal(bus, phy_addr, regnum);
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else
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phy_data = wx_phy_read_reg_mdi_c22(bus, phy_addr, regnum);
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return phy_data;
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}
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static int ngbe_phy_write_reg_c22(struct mii_bus *bus, int phy_addr,
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int regnum, u16 value)
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{
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struct wx *wx = bus->priv;
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int ret;
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if (wx->mac_type == em_mac_type_mdi)
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ret = ngbe_phy_write_reg_internal(bus, phy_addr, regnum, value);
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else
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ret = wx_phy_write_reg_mdi_c22(bus, phy_addr, regnum, value);
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return ret;
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}
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static void ngbe_mac_config(struct phylink_config *config, unsigned int mode,
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const struct phylink_link_state *state)
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{
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}
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static void ngbe_mac_link_down(struct phylink_config *config,
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unsigned int mode, phy_interface_t interface)
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{
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}
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static void ngbe_mac_link_up(struct phylink_config *config,
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struct phy_device *phy,
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unsigned int mode, phy_interface_t interface,
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int speed, int duplex,
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bool tx_pause, bool rx_pause)
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{
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struct wx *wx = phylink_to_wx(config);
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u32 lan_speed, reg;
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wx_fc_enable(wx, tx_pause, rx_pause);
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switch (speed) {
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case SPEED_10:
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lan_speed = 0;
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break;
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case SPEED_100:
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lan_speed = 1;
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break;
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case SPEED_1000:
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default:
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lan_speed = 2;
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break;
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}
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wr32m(wx, NGBE_CFG_LAN_SPEED, 0x3, lan_speed);
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reg = rd32(wx, WX_MAC_TX_CFG);
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reg &= ~WX_MAC_TX_CFG_SPEED_MASK;
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reg |= WX_MAC_TX_CFG_SPEED_1G | WX_MAC_TX_CFG_TE;
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wr32(wx, WX_MAC_TX_CFG, reg);
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/* Re configure MAC Rx */
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reg = rd32(wx, WX_MAC_RX_CFG);
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wr32(wx, WX_MAC_RX_CFG, reg);
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wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR);
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reg = rd32(wx, WX_MAC_WDG_TIMEOUT);
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wr32(wx, WX_MAC_WDG_TIMEOUT, reg);
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}
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static const struct phylink_mac_ops ngbe_mac_ops = {
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.mac_config = ngbe_mac_config,
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.mac_link_down = ngbe_mac_link_down,
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.mac_link_up = ngbe_mac_link_up,
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};
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static int ngbe_phylink_init(struct wx *wx)
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{
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struct phylink_config *config;
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phy_interface_t phy_mode;
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struct phylink *phylink;
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config = &wx->phylink_config;
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config->dev = &wx->netdev->dev;
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config->type = PHYLINK_NETDEV;
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config->mac_capabilities = MAC_1000FD | MAC_100FD | MAC_10FD |
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MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
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config->mac_managed_pm = true;
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phy_mode = PHY_INTERFACE_MODE_RGMII_ID;
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__set_bit(PHY_INTERFACE_MODE_RGMII_ID, config->supported_interfaces);
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phylink = phylink_create(config, NULL, phy_mode, &ngbe_mac_ops);
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if (IS_ERR(phylink))
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return PTR_ERR(phylink);
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wx->phylink = phylink;
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return 0;
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}
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int ngbe_mdio_init(struct wx *wx)
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{
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struct pci_dev *pdev = wx->pdev;
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struct mii_bus *mii_bus;
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int ret;
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mii_bus = devm_mdiobus_alloc(&pdev->dev);
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if (!mii_bus)
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return -ENOMEM;
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mii_bus->name = "ngbe_mii_bus";
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mii_bus->read = ngbe_phy_read_reg_c22;
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mii_bus->write = ngbe_phy_write_reg_c22;
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mii_bus->phy_mask = GENMASK(31, 4);
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mii_bus->parent = &pdev->dev;
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mii_bus->priv = wx;
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if (wx->mac_type == em_mac_type_rgmii) {
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mii_bus->read_c45 = wx_phy_read_reg_mdi_c45;
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mii_bus->write_c45 = wx_phy_write_reg_mdi_c45;
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}
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snprintf(mii_bus->id, MII_BUS_ID_SIZE, "ngbe-%x", pci_dev_id(pdev));
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ret = devm_mdiobus_register(&pdev->dev, mii_bus);
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if (ret)
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return ret;
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wx->phydev = phy_find_first(mii_bus);
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if (!wx->phydev)
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return -ENODEV;
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phy_attached_info(wx->phydev);
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wx->link = 0;
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wx->speed = 0;
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wx->duplex = 0;
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ret = ngbe_phylink_init(wx);
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if (ret) {
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wx_err(wx, "failed to init phylink: %d\n", ret);
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return ret;
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}
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return 0;
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}
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