337 lines
9.8 KiB
YAML
337 lines
9.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6xxx.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell MV88E6xxx DSA switch family
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maintainers:
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- Andrew Lunn <andrew@lunn.ch>
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description:
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The Marvell MV88E6xxx switch series has been produced and sold
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by Marvell since at least 2008. The switch has a few compatibles which
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just indicate the base address of the switch, then operating systems
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can investigate switch ID registers to find out which actual version
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of the switch it is dealing with.
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properties:
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compatible:
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oneOf:
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- enum:
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- marvell,mv88e6085
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- marvell,mv88e6190
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- marvell,mv88e6250
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description: |
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marvell,mv88e6085: This switch uses base address 0x10.
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This switch and its siblings will be autodetected from
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ID registers found in the switch, so only "marvell,mv88e6085" should be
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specified. This includes the following list of MV88Exxxx switches:
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6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165, 6171, 6172, 6175, 6176,
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6185, 6240, 6320, 6321, 6341, 6350, 6351, 6352
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marvell,mv88e6190: This switch uses base address 0x00.
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This switch and its siblings will be autodetected from
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ID registers found in the switch, so only "marvell,mv88e6190" should be
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specified. This includes the following list of MV88Exxxx switches:
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6190, 6190X, 6191, 6290, 6361, 6390, 6390X
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marvell,mv88e6250: This switch uses base address 0x08 or 0x18.
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This switch and its siblings will be autodetected from
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ID registers found in the switch, so only "marvell,mv88e6250" should be
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specified. This includes the following list of MV88Exxxx switches:
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6220, 6250
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- items:
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- const: marvell,turris-mox-mv88e6085
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- const: marvell,mv88e6085
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- items:
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- const: marvell,turris-mox-mv88e6190
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- const: marvell,mv88e6190
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reg:
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maxItems: 1
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eeprom-length:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Set to the length of an EEPROM connected to the switch. Must be
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set if the switch can not detect the presence and/or size of a connected
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EEPROM, otherwise optional.
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reset-gpios:
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description:
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GPIO to be used to reset the whole device
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maxItems: 1
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interrupts:
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description: The switch provides an external interrupt line, but it is
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not always used by target systems.
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maxItems: 1
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interrupt-controller:
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description: The switch has an internal interrupt controller used by
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the different sub-blocks.
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'#interrupt-cells':
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description: The internal interrupt controller only supports triggering
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on active high level interrupts so the second cell must alway be set to
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IRQ_TYPE_LEVEL_HIGH.
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const: 2
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mdio:
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$ref: /schemas/net/mdio.yaml#
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unevaluatedProperties: false
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description: Marvell MV88E6xxx switches have an varying combination of
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internal and external MDIO buses, in some cases a combined bus that
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can be used both internally and externally. This node is for the
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primary bus, used internally and sometimes also externally.
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mdio-external:
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$ref: /schemas/net/mdio.yaml#
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unevaluatedProperties: false
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description: Marvell MV88E6xxx switches that have a separate external
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MDIO bus use this port to access external components on the MDIO bus.
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properties:
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compatible:
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const: marvell,mv88e6xxx-mdio-external
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required:
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- compatible
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allOf:
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- $ref: dsa.yaml#/$defs/ethernet-ports
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-switch@0 {
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compatible = "marvell,mv88e6085";
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reg = <0>;
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reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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sw_phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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sw_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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sw_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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sw_phy3: ethernet-phy@3 {
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reg = <0x3>;
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};
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};
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-port@0 {
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reg = <0>;
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label = "lan4";
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phy-handle = <&sw_phy0>;
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phy-mode = "internal";
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};
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ethernet-port@1 {
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reg = <1>;
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label = "lan3";
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phy-handle = <&sw_phy1>;
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phy-mode = "internal";
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};
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ethernet-port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&sw_phy2>;
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phy-mode = "internal";
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};
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ethernet-port@3 {
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reg = <3>;
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label = "lan1";
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phy-handle = <&sw_phy3>;
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phy-mode = "internal";
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};
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ethernet-port@5 {
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reg = <5>;
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ethernet = <&fec>;
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phy-mode = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-switch@0 {
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compatible = "marvell,mv88e6190";
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gpio1>;
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interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-0 = <&switch_interrupt_pins>;
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pinctrl-names = "default";
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reg = <0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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switch0phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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switch0phy3: ethernet-phy@3 {
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reg = <0x3>;
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};
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switch0phy4: ethernet-phy@4 {
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reg = <0x4>;
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};
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switch0phy5: ethernet-phy@5 {
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reg = <0x5>;
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};
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switch0phy6: ethernet-phy@6 {
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reg = <0x6>;
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};
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switch0phy7: ethernet-phy@7 {
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reg = <0x7>;
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};
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switch0phy8: ethernet-phy@8 {
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reg = <0x8>;
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};
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};
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mdio-external {
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compatible = "marvell,mv88e6xxx-mdio-external";
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@b {
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reg = <0xb>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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phy2: ethernet-phy@c {
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reg = <0xc>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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};
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-port@0 {
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ethernet = <ð0>;
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phy-mode = "rgmii";
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reg = <0>;
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fixed-link {
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full-duplex;
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pause;
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speed = <1000>;
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};
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};
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ethernet-port@1 {
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label = "lan1";
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phy-handle = <&switch0phy1>;
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reg = <1>;
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};
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ethernet-port@2 {
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label = "lan2";
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phy-handle = <&switch0phy2>;
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reg = <2>;
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};
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ethernet-port@3 {
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label = "lan3";
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phy-handle = <&switch0phy3>;
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reg = <3>;
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};
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ethernet-port@4 {
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label = "lan4";
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phy-handle = <&switch0phy4>;
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reg = <4>;
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};
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ethernet-port@5 {
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label = "lan5";
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phy-handle = <&switch0phy5>;
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reg = <5>;
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};
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ethernet-port@6 {
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label = "lan6";
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phy-handle = <&switch0phy6>;
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reg = <6>;
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};
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ethernet-port@7 {
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label = "lan7";
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phy-handle = <&switch0phy7>;
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reg = <7>;
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};
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ethernet-port@8 {
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label = "lan8";
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phy-handle = <&switch0phy8>;
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reg = <8>;
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};
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ethernet-port@9 {
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/* 88X3310P external phy */
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label = "lan9";
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phy-handle = <&phy1>;
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phy-mode = "xaui";
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reg = <9>;
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};
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ethernet-port@a {
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/* 88X3310P external phy */
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label = "lan10";
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phy-handle = <&phy2>;
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phy-mode = "xaui";
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reg = <0xa>;
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};
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};
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};
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};
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